merged changes in pcie

fpga/lib/pcie/example/VCU108/fpga/fpga.xdc

@@ -28,6 +28,11 @@ set_property CONFIG_MODE BPI16                         [current_design]
 #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
 #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
 
+# User SMA clock J34/J35
+set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
+set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
+#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
+
 # LEDs
 set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
 set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]

fpga/lib/pcie/example/VCU108/fpga/rtl/fpga.v

@@ -32,6 +32,11 @@ THE SOFTWARE.
  * FPGA top-level module
  */
 module fpga (
+    /*
+     * Clock and reset
+     */
+    output wire       user_sma_clk_p,
+    output wire       user_sma_clk_n,
     /*
      * GPIO
      */
@@ -78,6 +83,14 @@ parameter BAR4_APERTURE = 16;
 wire pcie_user_clk;
 wire pcie_user_reset;
 
+// forward PCIe user clock out SMA connectors
+OBUFDS
+user_sma_clk_obufds_inst (
+    .I(pcie_user_clk),
+    .O(user_sma_clk_p),
+    .OB(user_sma_clk_n)
+);
+
 // GPIO
 wire btnu_int;
 wire btnl_int;

fpga/lib/pcie/example/VCU118/fpga/fpga.xdc

@@ -34,6 +34,11 @@ set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
 #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
 #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
 
+# User SMA clock J34/J35
+set_property -dict {LOC R32 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
+set_property -dict {LOC P32 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
+#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
+
 # LEDs
 set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
 set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]

fpga/lib/pcie/example/VCU118/fpga/rtl/fpga.v

@@ -32,6 +32,12 @@ THE SOFTWARE.
  * FPGA top-level module
  */
 module fpga (
+    /*
+     * Clock and reset
+     */
+    output wire        user_sma_clk_p,
+    output wire        user_sma_clk_n,
+
     /*
      * GPIO
      */
@@ -78,6 +84,14 @@ parameter BAR4_APERTURE = 16;
 wire pcie_user_clk;
 wire pcie_user_reset;
 
+// forward PCIe user clock out SMA connectors
+OBUFDS
+user_sma_clk_obufds_inst (
+    .I(pcie_user_clk),
+    .O(user_sma_clk_p),
+    .OB(user_sma_clk_n)
+);
+
 // GPIO
 wire btnu_int;
 wire btnl_int;

fpga/lib/pcie/rtl/dma_if_pcie_rd.v

@@ -632,8 +632,8 @@ always @* begin
     stat_rd_req_start_valid_next = 1'b0;
     stat_rd_op_table_full_next = op_tag_fifo_rd_ptr_reg == op_tag_fifo_wr_ptr_reg;
     stat_rd_no_tags_next = !req_pcie_tag_valid_reg;
-    stat_rd_tx_limit_next = !(!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg);
-    stat_rd_tx_stall_next = !(!tx_rd_req_tlp_valid_reg || tx_rd_req_tlp_ready);
+    stat_rd_tx_limit_next = (TX_SEQ_NUM_ENABLE && !active_tx_count_av_reg) || !active_cplh_fc_av_reg || !active_cpld_fc_av_reg;
+    stat_rd_tx_stall_next = tx_rd_req_tlp_valid_reg && !tx_rd_req_tlp_ready;
 
     req_pcie_addr_next = req_pcie_addr_reg;
     req_ram_sel_next = req_ram_sel_reg;

fpga/lib/pcie/rtl/dma_if_pcie_us.v

@@ -185,6 +185,8 @@ module dma_if_pcie_us #
     /*
      * Status
      */
+    output wire                                 status_rd_busy,
+    output wire                                 status_wr_busy,
     output wire                                 status_error_cor,
     output wire                                 status_error_uncor
 );
@@ -300,6 +302,7 @@ dma_if_pcie_us_rd_inst (
     /*
      * Status
      */
+    .status_busy(status_rd_busy),
     .status_error_cor(status_error_cor),
     .status_error_uncor(status_error_uncor)
 );
@@ -404,7 +407,12 @@ dma_if_pcie_us_wr_inst (
     .enable(write_enable),
     .requester_id(requester_id),
     .requester_id_enable(requester_id_enable),
-    .max_payload_size(max_payload_size)
+    .max_payload_size(max_payload_size),
+
+    /*
+     * Status
+     */
+    .status_busy(status_wr_busy)
 );
 
 endmodule

fpga/lib/pcie/rtl/dma_if_pcie_us_rd.v

@@ -150,6 +150,7 @@ module dma_if_pcie_us_rd #
     /*
      * Status
      */
+    output wire                                 status_busy,
     output wire                                 status_error_cor,
     output wire                                 status_error_uncor
 );
@@ -421,13 +422,22 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] active_tx_count_reg = {RQ_SEQ_NUM_WIDTH{1'b0}};
 reg active_tx_count_av_reg = 1'b1;
 reg inc_active_tx;
 
+reg [PCIE_TAG_WIDTH+1-1:0] active_tag_count_reg = 0;
+reg inc_active_tag;
+reg dec_active_tag;
+
+reg [OP_TAG_WIDTH+1-1:0] active_op_count_reg = 0;
+reg inc_active_op;
+reg dec_active_op;
+
 reg s_axis_rc_tready_reg = 1'b0, s_axis_rc_tready_next;
 reg s_axis_read_desc_ready_reg = 1'b0, s_axis_read_desc_ready_next;
 
 reg [TAG_WIDTH-1:0] m_axis_read_desc_status_tag_reg = {TAG_WIDTH{1'b0}}, m_axis_read_desc_status_tag_next;
 reg [3:0] m_axis_read_desc_status_error_reg = 4'd0, m_axis_read_desc_status_error_next;
 reg m_axis_read_desc_status_valid_reg = 1'b0, m_axis_read_desc_status_valid_next;
 
+reg status_busy_reg = 1'b0;
 reg status_error_cor_reg = 1'b0, status_error_cor_next;
 reg status_error_uncor_reg = 1'b0, status_error_uncor_next;
 
@@ -457,6 +467,7 @@ assign m_axis_read_desc_status_tag = m_axis_read_desc_status_tag_reg;
 assign m_axis_read_desc_status_error = m_axis_read_desc_status_error_reg;
 assign m_axis_read_desc_status_valid = m_axis_read_desc_status_valid_reg;
 
+assign status_busy = status_busy_reg;
 assign status_error_cor = status_error_cor_reg;
 assign status_error_uncor = status_error_uncor_reg;
 
@@ -577,6 +588,8 @@ always @* begin
     req_pcie_tag_valid_next = req_pcie_tag_valid_reg;
 
     inc_active_tx = 1'b0;
+    inc_active_tag = 1'b0;
+    inc_active_op = 1'b0;
 
     op_table_start_ptr = req_op_tag_reg;
     op_table_start_tag = s_axis_read_desc_tag;
@@ -728,6 +741,7 @@ always @* begin
                 op_table_start_ptr = req_op_tag_reg;
                 op_table_start_tag = s_axis_read_desc_tag;
                 op_table_start_en = 1'b1;
+                inc_active_op = 1'b1;
                 req_state_next = REQ_STATE_START;
             end else begin
                 req_state_next = REQ_STATE_IDLE;
@@ -750,6 +764,7 @@ always @* begin
                     pcie_tag_table_start_op_tag_next = req_op_tag_reg;
                     pcie_tag_table_start_zero_len_next = req_zero_len_reg;
                     pcie_tag_table_start_en_next = 1'b1;
+                    inc_active_tag = 1'b1;
 
                     op_table_read_start_ptr = req_op_tag_reg;
                     op_table_read_start_commit = req_last_tlp;
@@ -790,6 +805,7 @@ always @* begin
                     pcie_tag_table_start_op_tag_next = req_op_tag_reg;
                     pcie_tag_table_start_zero_len_next = req_zero_len_reg;
                     pcie_tag_table_start_en_next = 1'b1;
+                    inc_active_tag = 1'b1;
 
                     op_table_read_start_ptr = req_op_tag_reg;
                     op_table_read_start_commit = req_last_tlp;
@@ -877,6 +893,9 @@ always @* begin
 
     out_done_ack = {SEG_COUNT{1'b0}};
 
+    dec_active_tag = 1'b0;
+    dec_active_op = 1'b0;
+
     // Write generation
     ram_wr_cmd_sel_int = {SEG_COUNT{ram_sel_reg}};
     if (!ram_wrap_reg) begin
@@ -1381,6 +1400,7 @@ always @* begin
     end else if (finish_tag_reg) begin
         pcie_tag_table_finish_ptr = pcie_tag_reg;
         pcie_tag_table_finish_en = 1'b1;
+        dec_active_tag = 1'b1;
 
         pcie_tag_fifo_wr_tag = pcie_tag_reg;
         if (pcie_tag_fifo_wr_tag < PCIE_TAG_COUNT_1 || !PCIE_TAG_COUNT_2) begin
@@ -1440,6 +1460,7 @@ always @* begin
 
             if (op_table_read_commit[op_table_read_finish_ptr] && (op_table_read_count_start[op_table_read_finish_ptr] == op_table_read_count_finish[op_table_read_finish_ptr])) begin
                 op_tag_fifo_we = 1'b1;
+                dec_active_op = 1'b1;
                 m_axis_read_desc_status_valid_next = 1'b1;
             end
         end
@@ -1462,6 +1483,7 @@ always @(posedge clk) begin
         init_op_tag_reg <= init_count_reg + 1 < 2**OP_TAG_WIDTH;
     end
 
+    status_busy_reg <= active_op_count_reg != 0 || active_tx_count_reg != 0;
     status_error_cor_reg <= status_error_cor_next;
     status_error_uncor_reg <= status_error_uncor_next;
 
@@ -1554,6 +1576,9 @@ always @(posedge clk) begin
         active_tx_count_av_reg <= active_tx_count_reg < TX_LIMIT;
     end
 
+    active_tag_count_reg <= active_tag_count_reg + inc_active_tag - dec_active_tag;
+    active_op_count_reg <= active_op_count_reg + inc_active_op - dec_active_op;
+
     pcie_tag_table_start_ptr_reg <= pcie_tag_table_start_ptr_next;
     pcie_tag_table_start_ram_sel_reg <= pcie_tag_table_start_ram_sel_next;
     pcie_tag_table_start_ram_addr_reg <= pcie_tag_table_start_ram_addr_next;
@@ -1662,6 +1687,9 @@ always @(posedge clk) begin
         active_tx_count_reg <= {RQ_SEQ_NUM_WIDTH{1'b0}};
         active_tx_count_av_reg <= 1'b1;
 
+        active_tag_count_reg <= 0;
+        active_op_count_reg <= 0;
+
         pcie_tag_table_start_en_reg <= 1'b0;
 
         pcie_tag_fifo_1_wr_ptr_reg <= 0;
@@ -1672,6 +1700,7 @@ always @(posedge clk) begin
         op_tag_fifo_wr_ptr_reg <= 0;
         op_tag_fifo_rd_ptr_reg <= 0;
 
+        status_busy_reg <= 1'b0;
         status_error_cor_reg <= 1'b0;
         status_error_uncor_reg <= 1'b0;
     end

fpga/lib/pcie/rtl/dma_if_pcie_us_wr.v

@@ -149,7 +149,12 @@ module dma_if_pcie_us_wr #
     input  wire                                 enable,
     input  wire [15:0]                          requester_id,
     input  wire                                 requester_id_enable,
-    input  wire [2:0]                           max_payload_size
+    input  wire [2:0]                           max_payload_size,
+
+    /*
+     * Status
+     */
+    output wire                                 status_busy
 );
 
 parameter RAM_WORD_WIDTH = SEG_BE_WIDTH;
@@ -369,6 +374,10 @@ reg [RQ_SEQ_NUM_WIDTH-1:0] active_tx_count_reg = {RQ_SEQ_NUM_WIDTH{1'b0}};
 reg active_tx_count_av_reg = 1'b1;
 reg inc_active_tx;
 
+reg [OP_TAG_WIDTH+1-1:0] active_op_count_reg = 0;
+reg inc_active_op;
+reg dec_active_op;
+
 reg s_axis_rq_tready_reg = 1'b0, s_axis_rq_tready_next;
 
 reg s_axis_write_desc_ready_reg = 1'b0, s_axis_write_desc_ready_next;
@@ -381,6 +390,8 @@ reg [SEG_COUNT*SEG_ADDR_WIDTH-1:0] ram_rd_cmd_addr_reg = 0, ram_rd_cmd_addr_next
 reg [SEG_COUNT-1:0] ram_rd_cmd_valid_reg = 0, ram_rd_cmd_valid_next;
 reg [SEG_COUNT-1:0] ram_rd_resp_ready_cmb;
 
+reg status_busy_reg = 1'b0;
+
 // internal datapath
 reg  [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_rq_tdata_int;
 reg  [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_rq_tkeep_int;
@@ -410,6 +421,8 @@ assign ram_rd_cmd_addr = ram_rd_cmd_addr_reg;
 assign ram_rd_cmd_valid = ram_rd_cmd_valid_reg;
 assign ram_rd_resp_ready = ram_rd_resp_ready_cmb;
 
+assign status_busy = status_busy_reg;
+
 // operation tag management
 reg [OP_TAG_WIDTH+1-1:0] op_table_start_ptr_reg = 0;
 reg [PCIE_ADDR_WIDTH-1:0] op_table_start_pcie_addr;
@@ -498,6 +511,8 @@ always @* begin
     op_table_start_last = op_count_reg == tlp_count_reg;
     op_table_start_en = 1'b0;
 
+    inc_active_op = 1'b0;
+
     // TLP segmentation
     case (req_state_reg)
         REQ_STATE_IDLE: begin
@@ -578,6 +593,7 @@ always @* begin
 
                 op_table_start_tag = tag_reg;
                 op_table_start_en = 1'b1;
+                inc_active_op = 1'b1;
 
                 // TLP size computation
                 if (op_count_next <= {max_payload_size_dw_reg, 2'b00}-pcie_addr_next[1:0]) begin
@@ -805,6 +821,7 @@ always @* begin
     op_table_tx_finish_en = 1'b0;
 
     inc_active_tx = 1'b0;
+    dec_active_op = 1'b0;
 
     s_axis_rq_tready_next = 1'b0;
 
@@ -1174,6 +1191,7 @@ always @* begin
 
     if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && (!RQ_SEQ_NUM_ENABLE || op_table_tx_done[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) && op_table_finish_ptr_reg != op_table_tx_finish_ptr_reg) begin
         op_table_finish_en = 1'b1;
+        dec_active_op = 1'b1;
 
         if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
             m_axis_write_desc_status_valid_next = 1'b1;
@@ -1228,6 +1246,8 @@ always @(posedge clk) begin
     read_cmd_last_cycle_reg <= read_cmd_last_cycle_next;
     read_cmd_valid_reg <= read_cmd_valid_next;
 
+    status_busy_reg <= active_op_count_reg != 0 || active_tx_count_reg != 0;
+
     tlp_header_data_reg <= tlp_header_data_next;
     tlp_header_valid_reg <= tlp_header_valid_next;
     tlp_payload_data_reg <= tlp_payload_data_next;
@@ -1269,6 +1289,8 @@ always @(posedge clk) begin
         active_tx_count_av_reg <= active_tx_count_reg < TX_LIMIT;
     end
 
+    active_op_count_reg <= active_op_count_reg + inc_active_op - dec_active_op;
+
     if (mask_fifo_we) begin
         mask_fifo_mask[mask_fifo_wr_ptr_reg[MASK_FIFO_ADDR_WIDTH-1:0]] <= mask_fifo_wr_mask;
         mask_fifo_wr_ptr_reg <= mask_fifo_wr_ptr_reg + 1;
@@ -1331,6 +1353,8 @@ always @(posedge clk) begin
         active_tx_count_reg <= {RQ_SEQ_NUM_WIDTH{1'b0}};
         active_tx_count_av_reg <= 1'b1;
 
+        active_op_count_reg <= 0;
+
         mask_fifo_wr_ptr_reg <= 0;
         mask_fifo_rd_ptr_reg <= 0;
 

fpga/lib/pcie/rtl/dma_if_pcie_wr.v

@@ -479,8 +479,8 @@ always @* begin
     stat_wr_req_start_len_next = stat_wr_req_start_len_reg;
     stat_wr_req_start_valid_next = 1'b0;
     stat_wr_op_table_full_next = !(!op_table_active[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] && ($unsigned(op_table_start_ptr_reg - op_table_finish_ptr_reg) < 2**OP_TAG_WIDTH));
-    stat_wr_tx_limit_next = !(!TX_SEQ_NUM_ENABLE || active_tx_count_av_reg);
-    stat_wr_tx_stall_next = !(!tx_wr_req_tlp_valid_reg || tx_wr_req_tlp_ready);
+    stat_wr_tx_limit_next = (TX_SEQ_NUM_ENABLE && !active_tx_count_av_reg);
+    stat_wr_tx_stall_next = tx_wr_req_tlp_valid_reg && !tx_wr_req_tlp_ready;
 
     pcie_addr_next = pcie_addr_reg;
     ram_sel_next = ram_sel_reg;

fpga/lib/pcie/rtl/pcie_us_axi_dma.v

@@ -202,6 +202,8 @@ module pcie_us_axi_dma #
     /*
      * Status
      */
+    output wire                               status_rd_busy,
+    output wire                               status_wr_busy,
     output wire                               status_error_cor,
     output wire                               status_error_uncor
 );
@@ -327,6 +329,7 @@ pcie_us_axi_dma_rd_inst (
     /*
      * Status
      */
+    .status_busy(status_rd_busy),
     .status_error_cor(status_error_cor),
     .status_error_uncor(status_error_uncor)
 );
@@ -438,7 +441,12 @@ pcie_us_axi_dma_wr_inst (
     .enable(write_enable),
     .requester_id(requester_id),
     .requester_id_enable(requester_id_enable),
-    .max_payload_size(max_payload_size)
+    .max_payload_size(max_payload_size),
+
+    /*
+     * Status
+     */
+    .status_busy(status_wr_busy)
 );
 
 endmodule