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fpga: Split CMAC GTY channel RX clocking
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Signed-off-by: Alex Forencich <[email protected]>
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@alexforencich
alexforencich committed Oct 29, 2023
1 parent d78700d commit 65e4a97
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Showing 12 changed files with 23 additions and 51 deletions.
33 changes: 14 additions & 19 deletions fpga/common/rtl/cmac_gty_ch_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -100,9 +100,7 @@ module cmac_gty_ch_wrapper #
input wire [127:0] gt_txdata,
input wire [15:0] gt_txctrl0,
input wire [15:0] gt_txctrl1,
output wire gt_rxoutclk,
input wire gt_rxusrclk,
input wire gt_rxusrclk2,
output wire gt_rxusrclk2,
input wire rx_reset_in,
output wire rx_reset_done,
output wire gt_rx_reset_out,
Expand Down Expand Up @@ -141,6 +139,8 @@ wire tx_sel_pll_lock;
wire rx_sel_pll_lock;

// GT
wire gt_userclk_rx_active;

wire gt_tx_pma_reset_done;
wire gt_tx_prgdiv_reset_done;
wire gt_rx_pma_reset_done;
Expand Down Expand Up @@ -439,14 +439,7 @@ assign gt_rx_reset_out = gt_rx_reset_reg;

always @(posedge gt_rxusrclk2) begin
gt_rx_reset_done_reg <= gt_rx_reset_done;
end

always @(posedge gt_rxusrclk2, posedge gt_rx_reset_reg) begin
if (gt_rx_reset_reg) begin
gt_userclk_rx_active_reg <= 1'b0;
end else begin
gt_userclk_rx_active_reg <= 1'b1;
end
gt_userclk_rx_active_reg <= gt_userclk_rx_active;
end

always @(posedge drp_clk) begin
Expand Down Expand Up @@ -1015,11 +1008,12 @@ if (HAS_COMMON) begin : xcvr_gty_com
.txctrl1_in(gt_txctrl1),

// Receive
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active_reg),
.gtwiz_userclk_rx_reset_in(gt_rx_reset_reg),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(gt_rxusrclk2),
.gtwiz_userclk_rx_active_out(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done_reg),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk2),
.rxpd_in(gt_rx_pd_reg ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset_reg),
.rxpmareset_in(gt_rx_pma_reset_reg),
Expand Down Expand Up @@ -1126,11 +1120,12 @@ end else begin : xcvr_gty
.txctrl1_in(gt_txctrl1),

// Receive
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active_reg),
.gtwiz_userclk_rx_reset_in(gt_rx_reset_reg),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(gt_rxusrclk2),
.gtwiz_userclk_rx_active_out(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done_reg),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk2),
.rxpd_in(gt_rx_pd_reg ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset_reg),
.rxpmareset_in(gt_rx_pma_reset_reg),
Expand Down
22 changes: 0 additions & 22 deletions fpga/common/rtl/cmac_gty_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -810,7 +810,6 @@ wire [3:0] gt_rx_reset;
wire [3:0] gt_rx_reset_out;
wire gt_rxoutclk;
wire gt_rxoutclk_bufg;
wire [3:0] gt_rxusrclk;
wire [3:0] gt_rxusrclk2;

assign gt_tx_reset[0] = gt_tx_reset_drp_reg;
Expand All @@ -836,19 +835,6 @@ BUFG_GT bufg_gt_txusrclk_inst (
assign gt_txusrclk = gt_txoutclk_bufg;
assign gt_txusrclk2 = gt_txoutclk_bufg;

BUFG_GT bufg_gt_rxusrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset_out[0]),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxoutclk),
.O (gt_rxoutclk_bufg)
);

assign gt_rxusrclk = {4{gt_rxoutclk_bufg}};
assign gt_rxusrclk2 = {4{gt_rxoutclk_bufg}};

assign tx_clk = gt_txusrclk2;

wire tx_rst_int;
Expand Down Expand Up @@ -994,8 +980,6 @@ gty_ch_1 (
.gt_txdata(gt_txdata[0*128 +: 128]),
.gt_txctrl0(gt_txctrl0[0*16 +: 16]),
.gt_txctrl1(gt_txctrl1[0*16 +: 16]),
.gt_rxoutclk(gt_rxoutclk),
.gt_rxusrclk(gt_rxusrclk[0]),
.gt_rxusrclk2(gt_rxusrclk2[0]),
.rx_reset_in(gt_rx_reset[0]),
.rx_reset_done(gt_rx_reset_done[0]),
Expand Down Expand Up @@ -1075,8 +1059,6 @@ gty_ch_2 (
.gt_txdata(gt_txdata[1*128 +: 128]),
.gt_txctrl0(gt_txctrl0[1*16 +: 16]),
.gt_txctrl1(gt_txctrl1[1*16 +: 16]),
.gt_rxoutclk(),
.gt_rxusrclk(gt_rxusrclk[1]),
.gt_rxusrclk2(gt_rxusrclk2[1]),
.rx_reset_in(gt_rx_reset[1]),
.rx_reset_done(gt_rx_reset_done[1]),
Expand Down Expand Up @@ -1156,8 +1138,6 @@ gty_ch_3 (
.gt_txdata(gt_txdata[2*128 +: 128]),
.gt_txctrl0(gt_txctrl0[2*16 +: 16]),
.gt_txctrl1(gt_txctrl1[2*16 +: 16]),
.gt_rxoutclk(),
.gt_rxusrclk(gt_rxusrclk[2]),
.gt_rxusrclk2(gt_rxusrclk2[2]),
.rx_reset_in(gt_rx_reset[2]),
.rx_reset_done(gt_rx_reset_done[2]),
Expand Down Expand Up @@ -1237,8 +1217,6 @@ gty_ch_4 (
.gt_txdata(gt_txdata[3*128 +: 128]),
.gt_txctrl0(gt_txctrl0[3*16 +: 16]),
.gt_txctrl1(gt_txctrl1[3*16 +: 16]),
.gt_rxoutclk(),
.gt_rxusrclk(gt_rxusrclk[3]),
.gt_rxusrclk2(gt_rxusrclk2[3]),
.rx_reset_in(gt_rx_reset[3]),
.rx_reset_done(gt_rx_reset_done[3]),
Expand Down
1 change: 0 additions & 1 deletion fpga/common/syn/vivado/cmac_gty_ch_wrapper.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,6 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == cmac_gty_ch_wrapper ||
set_property -quiet ASYNC_REG TRUE [get_cells -quiet -hier -regexp ".*/gt_rxcdrlock_sync_\[12\]_reg_reg" -filter "PARENT == $inst"]

set_false_path -to [get_pins "$inst/gt_userclk_tx_active_reg_reg/CLR"]
set_false_path -to [get_pins "$inst/gt_userclk_rx_active_reg_reg/CLR"]

# TX
constrain_sync_chain $inst "gt_txprbssel_drp_reg_reg[*]" "gt_txprbssel_sync_reg_reg[*]"
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/250_SoC/fpga_100g/ip/cmac_gty.tcl
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Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/AU200/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/AU280/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/AU50/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/VCU118/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/XUPP3R/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/fb2CG/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down
2 changes: 1 addition & 1 deletion fpga/mqnic/fb4CGg3/fpga_100g/ip/cmac_gty.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}
Expand Down

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