fpga: Remove redundant RX PTP clock

Signed-off-by: Alex Forencich <[email protected]>
ucsdsysnet · Oct 28, 2023 · d78700d · d78700d
1 parent 6f2da7c
commit d78700d
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Showing 37 changed files with 27 additions and 253 deletions.
diff --git a/fpga/common/rtl/cmac_gty_wrapper.v b/fpga/common/rtl/cmac_gty_wrapper.v
@@ -145,8 +145,6 @@ module cmac_gty_wrapper #
     output wire                        rx_axis_tlast,
     output wire [80+1-1:0]             rx_axis_tuser,
 
-    output wire                        rx_ptp_clk,
-    output wire                        rx_ptp_rst,
     input  wire [79:0]                 rx_ptp_time,
 
     input  wire                        rx_enable,
@@ -903,17 +901,6 @@ end
 
 assign rx_rst = rx_rst_reg_2;
 
-assign rx_ptp_clk = gt_rxusrclk2[0];
-
-sync_reset #(
-    .N(4)
-)
-sync_reset_rx_ptp_rst_inst (
-    .clk(rx_ptp_clk),
-    .rst(gt_rx_reset_out[0] || rx_rst),
-    .out(rx_ptp_rst)
-);
-
 // serdes data
 // 80 bit mode - 64 bits in data, 8 bits each in ctrl0 and ctrl1 (per serdes)
 // widths match concatenated GTY ports (not all bits used)

diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
@@ -221,7 +221,6 @@ module fpga #
 parameter PTP_CLK_PERIOD_NS_NUM = 512;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
 parameter PTP_TS_WIDTH = 96;
-parameter PTP_SEPARATE_RX_CLOCK = 1;
 
 // Interface configuration
 parameter TX_TAG_WIDTH = 16;
@@ -708,8 +707,6 @@ wire                           qsfp0_rx_axis_tvalid_int;
 wire                           qsfp0_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp0_rx_axis_tuser_int;
 
-wire                           qsfp0_rx_ptp_clk_int;
-wire                           qsfp0_rx_ptp_rst_int;
 wire [79:0]                    qsfp0_rx_ptp_time_int;
 
 wire        qsfp0_drp_clk = clk_125mhz_int;
@@ -842,8 +839,6 @@ qsfp0_cmac_inst (
     .rx_axis_tlast(qsfp0_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp0_rx_axis_tuser_int),
 
-    .rx_ptp_clk(qsfp0_rx_ptp_clk_int),
-    .rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .rx_ptp_time(qsfp0_rx_ptp_time_int),
 
     .rx_enable(qsfp0_rx_enable),
@@ -881,8 +876,6 @@ wire                           qsfp1_rx_axis_tvalid_int;
 wire                           qsfp1_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp1_rx_axis_tuser_int;
 
-wire                           qsfp1_rx_ptp_clk_int;
-wire                           qsfp1_rx_ptp_rst_int;
 wire [79:0]                    qsfp1_rx_ptp_time_int;
 
 wire        qsfp1_drp_clk = clk_125mhz_int;
@@ -1015,8 +1008,6 @@ qsfp1_cmac_inst (
     .rx_axis_tlast(qsfp1_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp1_rx_axis_tuser_int),
 
-    .rx_ptp_clk(qsfp1_rx_ptp_clk_int),
-    .rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .rx_ptp_time(qsfp1_rx_ptp_time_int),
 
     .rx_enable(qsfp1_rx_enable),
@@ -1257,7 +1248,6 @@ fpga_core #(
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
-    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@@ -1525,8 +1515,6 @@ core_inst (
     .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int),
     .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int),
     .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int),
-    .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
-    .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
 
     .qsfp0_rx_enable(qsfp0_rx_enable),
@@ -1578,8 +1566,6 @@ core_inst (
     .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int),
     .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int),
     .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int),
-    .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
-    .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
 
     .qsfp1_rx_enable(qsfp1_rx_enable),

diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
-    parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
     parameter PTP_PEROUT_COUNT = 1,
@@ -312,8 +311,6 @@ module fpga_core #
     input  wire                               qsfp0_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp0_rx_axis_tuser,
 
-    input  wire                               qsfp0_rx_ptp_clk,
-    input  wire                               qsfp0_rx_ptp_rst,
     output wire [79:0]                        qsfp0_rx_ptp_time,
 
     output wire                               qsfp0_rx_enable,
@@ -369,8 +366,6 @@ module fpga_core #
     input  wire                               qsfp1_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp1_rx_axis_tuser,
 
-    input  wire                               qsfp1_rx_ptp_clk,
-    input  wire                               qsfp1_rx_ptp_rst,
     output wire [79:0]                        qsfp1_rx_ptp_time,
 
     output wire                               qsfp1_rx_enable,
@@ -877,8 +872,8 @@ mqnic_port_map_mac_axis_inst (
     .mac_rx_clk({qsfp1_rx_clk, qsfp0_rx_clk}),
     .mac_rx_rst({qsfp1_rx_rst, qsfp0_rx_rst}),
 
-    .mac_rx_ptp_clk({qsfp1_rx_ptp_clk, qsfp0_rx_ptp_clk}),
-    .mac_rx_ptp_rst({qsfp1_rx_ptp_rst, qsfp0_rx_ptp_rst}),
+    .mac_rx_ptp_clk(2'b00),
+    .mac_rx_ptp_rst(2'b00),
     .mac_rx_ptp_ts_96({qsfp1_rx_ptp_time_int, qsfp0_rx_ptp_time_int}),
     .mac_rx_ptp_ts_step(),
 
@@ -980,7 +975,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
-    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
+    .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile
@@ -125,7 +125,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 512
 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
 export PARAM_PTP_CLOCK_PIPELINE := 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
-export PARAM_PTP_SEPARATE_RX_CLOCK := 0
 export PARAM_PTP_PORT_CDC_PIPELINE := 0
 export PARAM_PTP_PEROUT_ENABLE := 0
 export PARAM_PTP_PEROUT_COUNT := 1

diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -689,7 +689,6 @@ def test_fpga_core(request):
     parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
-    parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
     parameters['PTP_PEROUT_COUNT'] = 1

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
@@ -248,7 +248,6 @@ module fpga #
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
 parameter PTP_TS_WIDTH = 96;
-parameter PTP_SEPARATE_RX_CLOCK = 1;
 
 // Interface configuration
 parameter TX_TAG_WIDTH = 16;
@@ -943,8 +942,6 @@ wire                           qsfp_0_rx_axis_tvalid_int;
 wire                           qsfp_0_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp_0_rx_axis_tuser_int;
 
-wire                           qsfp_0_rx_ptp_clk_int;
-wire                           qsfp_0_rx_ptp_rst_int;
 wire [79:0]                    qsfp_0_rx_ptp_time_int;
 
 wire        qsfp_0_drp_clk = clk_125mhz_int;
@@ -1077,8 +1074,6 @@ qsfp_0_cmac_inst (
     .rx_axis_tlast(qsfp_0_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp_0_rx_axis_tuser_int),
 
-    .rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
-    .rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
     .rx_ptp_time(qsfp_0_rx_ptp_time_int),
 
     .rx_enable(qsfp_0_rx_enable),
@@ -1116,8 +1111,6 @@ wire                           qsfp_1_rx_axis_tvalid_int;
 wire                           qsfp_1_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp_1_rx_axis_tuser_int;
 
-wire                           qsfp_1_rx_ptp_clk_int;
-wire                           qsfp_1_rx_ptp_rst_int;
 wire [79:0]                    qsfp_1_rx_ptp_time_int;
 
 wire        qsfp_1_drp_clk = clk_125mhz_int;
@@ -1250,8 +1243,6 @@ qsfp_1_cmac_inst (
     .rx_axis_tlast(qsfp_1_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp_1_rx_axis_tuser_int),
 
-    .rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
-    .rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
     .rx_ptp_time(qsfp_1_rx_ptp_time_int),
 
     .rx_enable(qsfp_1_rx_enable),
@@ -1617,7 +1608,6 @@ fpga_core #(
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
-    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@@ -1864,8 +1854,6 @@ core_inst (
     .qsfp_0_rx_axis_tvalid(qsfp_0_rx_axis_tvalid_int),
     .qsfp_0_rx_axis_tlast(qsfp_0_rx_axis_tlast_int),
     .qsfp_0_rx_axis_tuser(qsfp_0_rx_axis_tuser_int),
-    .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
-    .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
     .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int),
 
     .qsfp_0_rx_enable(qsfp_0_rx_enable),
@@ -1915,8 +1903,6 @@ core_inst (
     .qsfp_1_rx_axis_tvalid(qsfp_1_rx_axis_tvalid_int),
     .qsfp_1_rx_axis_tlast(qsfp_1_rx_axis_tlast_int),
     .qsfp_1_rx_axis_tuser(qsfp_1_rx_axis_tuser_int),
-    .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
-    .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
     .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int),
 
     .qsfp_1_rx_enable(qsfp_1_rx_enable),

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
@@ -40,7 +40,6 @@ module fpga_core #
     parameter PTP_TS_WIDTH = 96,
     parameter PTP_CLOCK_PIPELINE = 0,
     parameter PTP_CLOCK_CDC_PIPELINE = 0,
-    parameter PTP_SEPARATE_RX_CLOCK = 0,
     parameter PTP_PORT_CDC_PIPELINE = 0,
     parameter PTP_PEROUT_ENABLE = 0,
     parameter PTP_PEROUT_COUNT = 1,
@@ -291,8 +290,6 @@ module fpga_core #
     input  wire                               qsfp_0_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp_0_rx_axis_tuser,
 
-    input  wire                               qsfp_0_rx_ptp_clk,
-    input  wire                               qsfp_0_rx_ptp_rst,
     output wire [79:0]                        qsfp_0_rx_ptp_time,
 
     output wire                               qsfp_0_rx_enable,
@@ -346,8 +343,6 @@ module fpga_core #
     input  wire                               qsfp_1_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp_1_rx_axis_tuser,
 
-    input  wire                               qsfp_1_rx_ptp_clk,
-    input  wire                               qsfp_1_rx_ptp_rst,
     output wire [79:0]                        qsfp_1_rx_ptp_time,
 
     output wire                               qsfp_1_rx_enable,
@@ -967,8 +962,8 @@ mqnic_port_map_mac_axis_inst (
     .mac_rx_clk({qsfp_1_rx_clk, qsfp_0_rx_clk}),
     .mac_rx_rst({qsfp_1_rx_rst, qsfp_0_rx_rst}),
 
-    .mac_rx_ptp_clk({qsfp_1_rx_ptp_clk, qsfp_0_rx_ptp_clk}),
-    .mac_rx_ptp_rst({qsfp_1_rx_ptp_rst, qsfp_0_rx_ptp_rst}),
+    .mac_rx_ptp_clk(2'b00),
+    .mac_rx_ptp_rst(2'b00),
     .mac_rx_ptp_ts_96({qsfp_1_rx_ptp_time_int, qsfp_0_rx_ptp_time_int}),
     .mac_rx_ptp_ts_step(),
 
@@ -1070,7 +1065,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
-    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
+    .PTP_SEPARATE_RX_CLOCK(0),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
@@ -126,7 +126,6 @@ export PARAM_PTP_CLK_PERIOD_NS_NUM := 1024
 export PARAM_PTP_CLK_PERIOD_NS_DENOM := 165
 export PARAM_PTP_CLOCK_PIPELINE := 0
 export PARAM_PTP_CLOCK_CDC_PIPELINE := 0
-export PARAM_PTP_SEPARATE_RX_CLOCK := 0
 export PARAM_PTP_PORT_CDC_PIPELINE := 0
 export PARAM_PTP_PEROUT_ENABLE := 0
 export PARAM_PTP_PEROUT_COUNT := 1

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -692,7 +692,6 @@ def test_fpga_core(request):
     parameters['PTP_CLK_PERIOD_NS_DENOM'] = 165
     parameters['PTP_CLOCK_PIPELINE'] = 0
     parameters['PTP_CLOCK_CDC_PIPELINE'] = 0
-    parameters['PTP_SEPARATE_RX_CLOCK'] = 0
     parameters['PTP_PORT_CDC_PIPELINE'] = 0
     parameters['PTP_PEROUT_ENABLE'] = 0
     parameters['PTP_PEROUT_COUNT'] = 1

diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
@@ -282,7 +282,6 @@ module fpga #
 parameter PTP_CLK_PERIOD_NS_NUM = 1024;
 parameter PTP_CLK_PERIOD_NS_DENOM = 165;
 parameter PTP_TS_WIDTH = 96;
-parameter PTP_SEPARATE_RX_CLOCK = 1;
 
 // Interface configuration
 parameter TX_TAG_WIDTH = 16;
@@ -1123,8 +1122,6 @@ wire                           qsfp0_rx_axis_tvalid_int;
 wire                           qsfp0_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp0_rx_axis_tuser_int;
 
-wire                           qsfp0_rx_ptp_clk_int;
-wire                           qsfp0_rx_ptp_rst_int;
 wire [79:0]                    qsfp0_rx_ptp_time_int;
 
 wire        qsfp0_drp_clk = clk_125mhz_int;
@@ -1259,8 +1256,6 @@ qsfp0_cmac_inst (
     .rx_axis_tlast(qsfp0_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp0_rx_axis_tuser_int),
 
-    .rx_ptp_clk(qsfp0_rx_ptp_clk_int),
-    .rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .rx_ptp_time(qsfp0_rx_ptp_time_int),
 
     .rx_enable(qsfp0_rx_enable),
@@ -1301,8 +1296,6 @@ wire                           qsfp1_rx_axis_tvalid_int;
 wire                           qsfp1_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp1_rx_axis_tuser_int;
 
-wire                           qsfp1_rx_ptp_clk_int;
-wire                           qsfp1_rx_ptp_rst_int;
 wire [79:0]                    qsfp1_rx_ptp_time_int;
 
 wire        qsfp1_drp_clk = clk_125mhz_int;
@@ -1435,8 +1428,6 @@ qsfp1_cmac_inst (
     .rx_axis_tlast(qsfp1_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp1_rx_axis_tuser_int),
 
-    .rx_ptp_clk(qsfp1_rx_ptp_clk_int),
-    .rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .rx_ptp_time(qsfp1_rx_ptp_time_int),
 
     .rx_enable(qsfp1_rx_enable),
@@ -2046,7 +2037,6 @@ fpga_core #(
     .PTP_TS_WIDTH(PTP_TS_WIDTH),
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
-    .PTP_SEPARATE_RX_CLOCK(PTP_SEPARATE_RX_CLOCK),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@@ -2301,8 +2291,6 @@ core_inst (
     .qsfp0_rx_axis_tvalid(qsfp0_rx_axis_tvalid_int),
     .qsfp0_rx_axis_tlast(qsfp0_rx_axis_tlast_int),
     .qsfp0_rx_axis_tuser(qsfp0_rx_axis_tuser_int),
-    .qsfp0_rx_ptp_clk(qsfp0_rx_ptp_clk_int),
-    .qsfp0_rx_ptp_rst(qsfp0_rx_ptp_rst_int),
     .qsfp0_rx_ptp_time(qsfp0_rx_ptp_time_int),
 
     .qsfp0_rx_enable(qsfp0_rx_enable),
@@ -2355,8 +2343,6 @@ core_inst (
     .qsfp1_rx_axis_tvalid(qsfp1_rx_axis_tvalid_int),
     .qsfp1_rx_axis_tlast(qsfp1_rx_axis_tlast_int),
     .qsfp1_rx_axis_tuser(qsfp1_rx_axis_tuser_int),
-    .qsfp1_rx_ptp_clk(qsfp1_rx_ptp_clk_int),
-    .qsfp1_rx_ptp_rst(qsfp1_rx_ptp_rst_int),
     .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int),
 
     .qsfp1_rx_enable(qsfp1_rx_enable),