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Issues list

Question about Transmitting an executable binary to FPGA via Serial port enhancement
#2151 opened Dec 12, 2024 by yueca
2 tasks done
Failed to ./build-setup.sh at conda setup VerificationError on open_pdk packages. bug
#2147 opened Dec 6, 2024 by trustfarm-dev
3 tasks done
2
NVDLA cannot read cache data correctly bug
#2137 opened Nov 29, 2024 by franktaTian
3 tasks done
2
basic design fail to meet timing and a really slow booting linux on VCU118 bug
#2119 opened Nov 8, 2024 by Charles-Tang
3 tasks done
5
i want to build a customed SOC bitstream in chipyard /FPGA enhancement
#2102 opened Oct 28, 2024 by cinder023
2 tasks done
3
How to configure asynchronous reset enhancement
#2098 opened Oct 25, 2024 by AD738560581
2 tasks done
5
Error: Failed to make rmapats.so bug
#2091 opened Oct 21, 2024 by RockyQLuo
3 tasks done
2
Numpy-1.26.4-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl is not a supported wheel on this platform bug
#2080 opened Oct 12, 2024 by ZechenM
3 tasks done
FireSim doesn't work with cloned configs + CloneLazyModule caveats bug
#2076 opened Oct 8, 2024 by abejgonzalez
3 tasks done
1
Add documentation for required dependencies and fix build-setup.sh issues enhancement
#2073 opened Oct 6, 2024 by StephenMoreOSU
2 tasks done
./build-setup.sh riscv-tools error bug
#2065 opened Sep 30, 2024 by RockyQLuo
3 tasks done
6
firesim debug：using config (Rocket chip+custom Axi4 Peripheral) on fpga, segmentation faullt occurs when accessing Specific peripheral address bug
#2062 opened Sep 26, 2024 by huchensong
3 tasks done
Sky130 + openroad documentation doesn't work bug
#2059 opened Sep 23, 2024 by arunlee77
3 tasks done
The current default IOBinder for Debug Module does not punch out the ndreset (and hartResetReq)? bug
#2048 opened Sep 15, 2024 by DecodeTheEncoded
3 tasks done
4
How to export my custom IO signals at RocketTile module to DigitalTop's IO? enhancement
#2046 opened Sep 14, 2024 by csgxiong
2 tasks done
2
Error while executing "make buildfile CONFIG=GemminiRocketConfig tutorial=sky130-openroad" bug
#2035 opened Sep 7, 2024 by chihyu-box
3 tasks done
2
How to Add a prefix at every module name when generating system verilog? enhancement
#2033 opened Sep 6, 2024 by csgxiong
2 tasks done
1
VLSI Flow broken for OpenRoad+Sky130 on chipyard 1.11.0 or above? bug
#2017 opened Aug 26, 2024 by Jerry-Tianchen
3 tasks done
Build-setup issue bug
#2016 opened Aug 26, 2024 by alsrbok
3 tasks done
4
build-setup.sh $(which conda) returns function bug
#2002 opened Aug 15, 2024 by allpan3
3 tasks done
1
Verilator simulations can be made an order of magnitude faster enhancement
#2000 opened Aug 13, 2024 by mayyxeng
2 tasks done
3
Program runs extremely slow on VCU118 for larger testcases bug
#1992 opened Aug 11, 2024 by Nerotos
3 tasks done
Error while running the coremark on largeBoomcore in chipyard bug
#1989 opened Aug 9, 2024 by waseem-10xe
3 tasks done
1
RoCC Punch Trough Signal enhancement
#1987 opened Aug 9, 2024 by eric900115
2 tasks done
6
ASAP7 + OpenRoad. ERROR: Can't open ABC output file. bug
#1936 opened Aug 1, 2024 by exhaust-create
3 tasks done
3
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