Senior Year - First Term - Faculty of Engineering Helwan University - Repository

Internship at VSD on RISC-V and VLSI using VSDSquadron Mini Board

Path-Oriented Decision Making (PODEM) algorithm for Automatic Test Pattern Generation (ATPG).

Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)

VHDL Implementations:logic Gates, Flip-Flops, Adders, Mux, and Encoders/Decoder This repository contains VHDL implementations of essential digital circuits used in FPGA and ASIC design .This repository is useful for digital design projects and for understanding different VHDL modeling styles: behavioral, structural, and dataflow.

VLSI Conference Dates

Sobre mim

This is my MSc thesis project published in the University of Guelph library. This project applies Graph Neural Networks, to an optimization problem, Circuit Partitioning, leveraging, the predictive power of deep learning instead of traditional techniques.

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

Summer School on Full Stack Open-Source Ecosystem for Processor Based Chip Design

The repository contains an analysis and tapeout design process of a CMOS inverter under sky130 PDK. open source tools like Ngspice, Magic VLSI, Xschem has been used for design and simulations.

A collection of Schematics, PCBs and VLSI work on various platforms

Gatery, a library for circuit design.

This repository contains a collection of basic VHDL programs, including implementations of fundamental electronic components such as logic gates, flip-flops, adders, counters, subtractors, and more.

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

VLSI Project for CMPE 480______ Authors: John San Juan, Cody Hum, Vincent Verdan, Jose Zaragosa

This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.

This repository contains code files for VLSI Laboratory - EC39004, conducted in Spring 2024 at IIT Kharagpur