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ammarmalik17 / Verilog_Adders

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This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
  • Updated Aug 24, 2024
  • Verilog

PoulamiSarkar24 / VHDL

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This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.

vhdl mux half-adder vhdl-code vhdl-examples full-adder ripple-carry-adder basic-gates-vhdl universal-gates-vhdl de-mux composite-adder encoder-vhdl decoder-vhdl carry-look-ahead-adder-vhdl
  • Updated Jul 9, 2024
  • VHDL

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