SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
python
flow
simulator
tdd
simulation
foss
verilog
testcase
tdd-utilities
mit-license
systemverilog
icarus-verilog
gtkwave
verification-methodologies
vcd
verilator
svut
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Updated
Sep 24, 2024 - Python