《30天自制操作系统》源码中文版。自己制作一个操作系统（OSASK）的过程

Must-have verilog systemverilog modules

Redis Simple Message Queue

Lightweight generic ring buffer manager library

A collection of lock-free data structures written in standard C++11

Arduino and CMake library for communicating with the InvenSense MPU-6500, MPU-9250 and MPU-9255 nine-axis IMUs.

Tutorial "Weeks of debugging can save you hours of TLA+". Each git commit introduces a new concept => check the git history!

A key:value store/cache library written in Go generics. LRU, LFU, FIFO, MRU, Clock support.

A caching library for Python

simple C++11 ring buffer implementation, allocated and evaluated at compile time

Go concurrent-safe, goroutine-safe, thread-safe queue

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

C++ cache with LRU/LFU/FIFO policies implementation

STM32串口DMA模式发送&接收实现，高速串口通信（1.5Mbps）不丢数据

A fast, reliable Redis-backed per-group FIFO queue for Node + TypeScript with guaranteed job ordering and parallel processing across groups.

Elixir queue! A simple, in-memory queue with worker pooling and rate limiting in Elixir.

a high performance library for building cache simulators

A fast, generic fifo for MCUs.

A powerful caching library for Python, with TTL support and multiple algorithm options.

multi-sdr-gps-sim generates a IQ data stream on-the-fly to simulate a GPS L1 baseband signal using a SDR platform like HackRF or ADLAM-Pluto.