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1st-CLaaS Kernel in WARP-V Configurator #115

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12 changes: 10 additions & 2 deletions configurator/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,15 @@ This project was bootstrapped with [Create React App](https://github.com/faceboo

## Available Scripts

In the project directory, you can run:
In the project directory, you can first install npm:

```
sudo apt install npm
```
To install yarn
```
sudo npm install --global yarn
```

### `yarn`

Expand All @@ -11,7 +19,7 @@ Once to install.
### `yarn start`

Runs the app in the development mode.<br />
Open [http://localhost:3000](http://localhost:3000) to view it in the browser.
Open [http://localhost:3009](http://localhost:3009) to view it in the browser.

The page will reload if you make edits.<br />
You will also see any lint errors in the console.
Expand Down
13 changes: 5 additions & 8 deletions configurator/src/components/pages/ConfigureCpuComponent.js
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,7 @@ export function ConfigureCpuComponent({
<Tab>Pipeline</Tab>
<Tab>Components</Tab>
<Tab>Hazards</Tab>
<Tab>Memory</Tab>
<Tab>I/O</Tab>
<Tab>Target</Tab>
<Tab>Verilog</Tab>
<Tab>Program</Tab>
</TabList>
Expand Down Expand Up @@ -70,11 +69,9 @@ export function ConfigureCpuComponent({
configurationParametersSubset={hazardsParams}/>
</TabPanel>
<TabPanel>
<Text>WARP-V currently supports only the CPU core itself, with a small instruction memory and
data memory.</Text>
</TabPanel>
<TabPanel>
<Text>WARP-V does not currently provide any I/O components.</Text>
<GenericSettingsFormComponent configuratorGlobalSettings={configuratorGlobalSettings}
setConfiguratorGlobalSettings={setConfiguratorGlobalSettings}
configurationParametersSubset={["target_plat"]}/>
</TabPanel>
<TabPanel>
<VerilogSettingsForm generalSettings={generalSettings}
Expand All @@ -91,4 +88,4 @@ export function ConfigureCpuComponent({
</TabPanels>
</Tabs>
</Box>;
}
}
6 changes: 3 additions & 3 deletions configurator/src/components/pages/WarpVPageBase.js
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ export function WarpVPageBase({
setTlvForJson(null)
} else {
const macros = translateJsonToM4Macros(coreJson)
const tlv = getTLVCodeForDefinitions(macros, configuratorCustomProgramName, programText, configuratorGlobalSettings.generalSettings.isa, configuratorGlobalSettings.generalSettings)
const tlv = getTLVCodeForDefinitions(macros, configuratorCustomProgramName, programText, configuratorGlobalSettings.generalSettings.isa, configuratorGlobalSettings.generalSettings, configuratorGlobalSettings.settings.target_plat )
setMacrosForJson(tlv.split("\n"))

const task = setTimeout(() => {
Expand Down Expand Up @@ -238,7 +238,7 @@ export function WarpVPageBase({
if (validateForm(true)) {
setMakerchipOpening(true)
const macros = translateJsonToM4Macros(coreJson);
const tlv = getTLVCodeForDefinitions(macros, configuratorCustomProgramName, programText, configuratorGlobalSettings.generalSettings.isa, configuratorGlobalSettings.generalSettings);
const tlv = getTLVCodeForDefinitions(macros, configuratorCustomProgramName, programText, configuratorGlobalSettings.generalSettings.isa, configuratorGlobalSettings.generalSettings, configuratorGlobalSettings.settings.target_plat);
openInMakerchip(tlv, setMakerchipOpening, setDisclosureAndUrl)
}
}
Expand All @@ -252,7 +252,7 @@ export function WarpVPageBase({
})
setDownloadingCode(true)
const macros = translateJsonToM4Macros(coreJson);
const tlv = getTLVCodeForDefinitions(macros, configuratorCustomProgramName, programText, configuratorGlobalSettings.generalSettings.isa, configuratorGlobalSettings.generalSettings);
const tlv = getTLVCodeForDefinitions(macros, configuratorCustomProgramName, programText, configuratorGlobalSettings.generalSettings.isa, configuratorGlobalSettings.generalSettings, configuratorGlobalSettings.settings.target_plat);
getSVForTlv(tlv, sv => {
downloadOrCopyFile(false, 'verilog.sv', sv);
setDownloadingCode(false)
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -91,6 +91,18 @@ export const ConfigurationParameters = [
validator: (input, setting) => setting.possibleValues.includes(input),
configurationCategory: "CPU"
},
{
macroType: "var",
readableName: "Target Platform",
verilogName: "TARGET_PLATFORM",
defaultValue: "None",
jsonKey: "target_plat",
type: RadioParameter,
possibleValues: ["1st-CLaaS", "Tinytapeout"],
validator: (input, setting) => setting.possibleValues.includes(input),
description: "Target platform consists of FPGA (included in 1st-CLaaS) and ASIC (included in Tinytapeout)",
configurationCategory: "CPU"
},
{
macroType: "var",
readableName: "EXTRA_REPLAY_BUBBLE",
Expand Down Expand Up @@ -294,4 +306,4 @@ export const ConfigurationParameters = [
configurationCategory: "CPU",
description: "Alignment of load return pseudo-instruction into |mem pipeline. If |mem stages reflect nominal alignment w/ load instruction, this is the nominal load latency."
},
]
]
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