Skip to content
View stevehoover's full-sized avatar

Block or report stevehoover

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. LF-Building-a-RISC-V-CPU-Core LF-Building-a-RISC-V-CPU-Core Public

    TL-Verilog 352 182

  2. warp-v warp-v Public

    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    TL-Verilog 231 57

  3. RISC-V_MYTH_Workshop RISC-V_MYTH_Workshop Public template

    Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

    TL-Verilog 78 32

  4. makerchip_examples makerchip_examples Public

    TL-Verilog 15 7

  5. MYTH_Workshop_Assignments MYTH_Workshop_Assignments Public template

    Starting-point template for students in the Microprocessor for You in Thirty Hours Workshop

    9 7

  6. LF-Building-a-RISC-V-CPU-Core-Course LF-Building-a-RISC-V-CPU-Core-Course Public

    The Linux Foundation/Redwood EDA "Building a RISC-V CPU" Course content, also available via EdX.

    Python 8 2