TL-Verilog Makerchip Examples

Various examples of TL-Verilog code to run in Makerchip.com.

Here are some quick-links:

From other repos:

Name		Name	Last commit message	Last commit date
Latest commit History 122 Commits
tiny_tapeout_examples		tiny_tapeout_examples
viz_imgs		viz_imgs
.gitignore		.gitignore
1st-claas_template_no_macros.tlv		1st-claas_template_no_macros.tlv
1st-claas_template_with_macros.tlv		1st-claas_template_with_macros.tlv
DAC_ring_example.tlv		DAC_ring_example.tlv
LICENSE.md		LICENSE.md
README.md		README.md
WIP_SERV_ALU.tlv		WIP_SERV_ALU.tlv
WIP_nand_challenge.tlv		WIP_nand_challenge.tlv
WIP_warp_with_bypass_macro.tlv		WIP_warp_with_bypass_macro.tlv
all_examples.tlv		all_examples.tlv
basic_logic_examples.tlv		basic_logic_examples.tlv
caravel_example.tlv		caravel_example.tlv
dac_ring_diagrams.tlv		dac_ring_diagrams.tlv
dac_ring_tlv_vs_rtl.tlv		dac_ring_tlv_vs_rtl.tlv
elevator.tlv		elevator.tlv
flow_example_basejump_viz.tlv		flow_example_basejump_viz.tlv
frog_maze.tlv		frog_maze.tlv
life_minimal.tlv		life_minimal.tlv
life_sv_viz.tlv		life_sv_viz.tlv
life_viz.tlv		life_viz.tlv
logic_gates.tlv		logic_gates.tlv
makerchip.json		makerchip.json
mandelbrot_as_img.tlv		mandelbrot_as_img.tlv
mandelbrot_synthesizable.tlv		mandelbrot_synthesizable.tlv
mandelbrot_wip.tlv		mandelbrot_wip.tlv
neural_network_viz.tlv		neural_network_viz.tlv
pythagoras_viz.tlv		pythagoras_viz.tlv
ring_viz.tlv		ring_viz.tlv
ripple_carry.tlv		ripple_carry.tlv
router_order_checker.tlv		router_order_checker.tlv
serv.tlv		serv.tlv
simple_m5.tlv		simple_m5.tlv
smith_waterman.tlv		smith_waterman.tlv
sort_viz.tlv		sort_viz.tlv
tree_redux.tlv		tree_redux.tlv
uw_ece755.tlv		uw_ece755.tlv
viz.tlv		viz.tlv
viz_demo.tlv		viz_demo.tlv

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