Files
ae350_customized_demo
Folders and files
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RiscV_AE350_SOC FPGA Reference Design Read Me File
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Frequency
CORE clock : 800MHz
DDR clock : 50MHz
AHB clock : 100MHz
APB clock : 100MHz
RTC clock : 10MHz
DDR3 memory clock : 200MHz
DDR3 input clock : 50MHz
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Platform
Tang_MEGA_138K_Pro_Dock
GW5AST-LV138FPG676AES
GW5AST-138
B
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Demo
ae350_demo
ae350_customized_demo
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Configuration
Embedded Instruction Memory
Embedded Data Memory
PIT
UART2
GPIO
WDT
RTC
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IDE
Version tested: Gowin_V1.9.9 (64-bit)
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