Add new Tier 3 targets for ARMv6 #150138
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,29 @@ | ||
| //! Targets the ARMv6K architecture, with `a32` code by default. | ||
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| use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs}; | ||
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| pub(crate) fn target() -> Target { | ||
| Target { | ||
| llvm_target: "armv6-none-eabi".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Bare ARMv6 soft-float".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 32, | ||
| arch: Arch::Arm, | ||
| data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), | ||
| options: TargetOptions { | ||
| abi: Abi::Eabi, | ||
| llvm_floatabi: Some(FloatAbi::Soft), | ||
| asm_args: cvs!["-mthumb-interwork", "-march=armv6", "-mlittle-endian",], | ||
| features: "+soft-float,+strict-align,+v6k".into(), | ||
| atomic_cas: true, | ||
| has_thumb_interworking: true, | ||
| // LDREXD/STREXD available as of ARMv6K | ||
| max_atomic_width: Some(64), | ||
| ..base::arm_none::opts() | ||
| }, | ||
| } | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,29 @@ | ||
| //! Targets the ARMv6K architecture, with `a32` code by default, and hard-float ABI | ||
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| use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs}; | ||
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| pub(crate) fn target() -> Target { | ||
| Target { | ||
| llvm_target: "armv6-none-eabihf".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Bare ARMv6 hard-float".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 32, | ||
| arch: Arch::Arm, | ||
| data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), | ||
| options: TargetOptions { | ||
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| abi: Abi::EabiHf, | ||
| llvm_floatabi: Some(FloatAbi::Hard), | ||
| asm_args: cvs!["-mthumb-interwork", "-march=armv6", "-mlittle-endian",], | ||
| features: "+strict-align,+v6k,+vfp2,-d32".into(), | ||
| atomic_cas: true, | ||
| has_thumb_interworking: true, | ||
| // LDREXD/STREXD available as of ARMv6K | ||
| max_atomic_width: Some(64), | ||
| ..base::arm_none::opts() | ||
| }, | ||
| } | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,29 @@ | ||
| //! Targets the ARMv6K architecture, with `t32` code by default. | ||
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| use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base, cvs}; | ||
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| pub(crate) fn target() -> Target { | ||
| Target { | ||
| llvm_target: "thumbv6-none-eabi".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Thumb-mode Bare ARMv6 soft-float".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 32, | ||
| arch: Arch::Arm, | ||
| data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), | ||
| options: TargetOptions { | ||
| abi: Abi::Eabi, | ||
| llvm_floatabi: Some(FloatAbi::Soft), | ||
| asm_args: cvs!["-mthumb-interwork", "-march=armv6", "-mlittle-endian",], | ||
| features: "+soft-float,+strict-align,+v6k".into(), | ||
| // atomics not available until ARMv6T2 | ||
| atomic_cas: false, | ||
| max_atomic_width: Some(0), | ||
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Member
There was a problem hiding this comment. I suspect this can be implemented using thumb interworking. (If so, I'm not sure if LLVM implements it, but I think I can implement it in portable-atomic.)
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There was a problem hiding this comment. What do you suggest I change it to?
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There was a problem hiding this comment. I tried So for the same reason as ARMv4T and ARMv5TE I propose just switching atomics off here, and letting portable-atomic provide a work-around if it so chooses.
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Thanks for confirming. LLVM just generates I believe more appropriate approach here is to implement the
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Opened rust-lang/compiler-builtins#1050 which implements this approach. If you and the compiler-builtins maintainer are okay with that approach, we can set the max-atomic-width to 32 and atomic-cas to true for thumbv6-none-eabi after the new compiler-builtins version containing that change is released. |
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| has_thumb_interworking: true, | ||
| ..base::arm_none::opts() | ||
| }, | ||
| } | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
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| # `armv6-none-eabi*` and `thumbv6-none-eabi` | ||
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| * **Tier: 3** | ||
| * **Library Support:** core and alloc (bare-metal, `#![no_std]`) | ||
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| Bare-metal target for any cpu in the Armv6 architecture family, supporting | ||
| ARM/Thumb code interworking (aka `Arm`/`Thumb`), with `Arm` code as the default | ||
| code generation. The most common processor family using the Armv6 architecture | ||
| is the ARM11, which includes the ARM1176JZF-S used in the original Raspberry Pi | ||
| and in the Raspberry Pi Zero. | ||
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| This target assumes your processor has the Armv6K extensions, as basically all | ||
| Armv6 processors do[^1]. The Armv6K extension adds the `LDREXB` and `STREXB` | ||
| instructions required to efficiently implement CAS on the [`AtomicU8`] and | ||
| [`AtomicI8`] types. | ||
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| The `thumbv6-none-eabi` target is the same as this one, but the instruction set | ||
| defaults to `Thumb`. Note that this target only supports the old Thumb-1 | ||
| instruction set, not the later Thumb-2 instruction set that was added in the | ||
| Armv6T2 extension. Note that the Thumb-1 instruction set does not support | ||
| atomics. | ||
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| The `armv6-none-eabihf` target uses the EABIHF hard-float ABI, and requires an | ||
| FPU - it assumes a VFP2D16 FPU is present. The FPU is not available from Thumb | ||
| mode so there is no `thumbv6-none-eabihf` target. | ||
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| See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all | ||
| `arm-none-eabi` targets. | ||
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| [`AtomicU8`]: https://docs.rust-lang.org/stable/core/sync/atomic/struct.AtomicU8.html | ||
| [`AtomicI8`]: https://docs.rust-lang.org/stable/core/sync/atomic/struct.AtomicI8.html | ||
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| ## Target Maintainers | ||
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| [@thejpster](https://github.com/thejpster) | ||
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| [^1]: The only ARMv6 processor without the Armv6k extensions is the first (r0) | ||
| revision of the ARM1136 - in the unlikely event you have a chip with one of | ||
| these processors, use the ARMv5TE target instead. |
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