Add new Tier 3 targets for ARMv6

[thejpster]

Adds three new targets to support ARMv6 processors running bare-metal:

• armv6-none-eabi - Arm ISA, soft-float
• armv6-none-eabihf - Arm ISA, hard-float
• thumbv6-none-eabi - Thumb-1 ISA, soft-float

There is no thumbv6-none-eabihf target because as far as I can tell, hard-float isn't support with the Thumb-1 instruction set (and you need the ARMv6T2 extension to enable Thumb-2 support).

The targets require ARMv6K as a minimum, which allows the two Arm ISA targets to have full CAS atomics. LLVM has a bug which means it emits some ARMv6K instructions even if you only call for ARMv6, and as no-one else has noticed the bug, and because basically all ARMv6 processors have ARMv6K, I think this is fine. The Thumb target also doesn't have any kind of atomics, just like the Armv5TE and Armv4 targets, because LLVM was emitting library calls to emulate them.

Testing will be added to https://github.com/rust-embedded/aarch32 once the target is accepted. I already have tests for the other non-M arm-none-eabi targets, and those tests pass on these targets.

A tier 3 target must have a designated developer or developers (the "target maintainers") on record to be CCed when issues arise regarding the target. (The mechanism to track and CC such developers may evolve over time.)

I have listed myself. If accepted, I'll talk to the Embedded Devices Working Group about adding this one to the rosta with all the others they support.

Targets must use naming consistent with any existing targets; for instance, a target for the same CPU or OS as an existing Rust target should use the same name for that CPU or OS. Targets should normally use the same names and naming conventions as used elsewhere in the broader ecosystem beyond Rust (such as in other toolchains), unless they have a very good reason to diverge. Changing the name of a target can be highly disruptive, especially once the target reaches a higher tier, so getting the name right is important even for a tier 3 target.

You might prefer arm-none-eabi, because arm-unknown-linux-gnu is an ARMv6 target - the implicit rule seems to be that if the Arm architecture version isn't specified, it's assumed to be v6. However, armv6-none-eabi seemed to fit better between armv5te-none-eabi and armv7a/armv7r-none-eabi.

The hamming distance between thumbv6-none-eabi and thumbv6m-none-eabi is unfortunately low, but I don't know how to make it better. They are the ARMv6 and ARMv6-M targets, and its perhaps not worse than armv7a-none-eabi and armv7r-none-eabi.

Tier 3 targets may have unusual requirements to build or use, but must not create legal issues or impose onerous legal terms for the Rust project or for Rust developers or users.

No different to any other arm-none-eabi target.

Neither this policy nor any decisions made regarding targets shall create any binding agreement or estoppel by any party. If any member of an approving Rust team serves as one of the maintainers of a target, or has any legal or employment requirement (explicit or implicit) that might affect their decisions regarding a target, they must recuse themselves from any approval decisions regarding the target's tier status, though they may otherwise participate in discussions.

Noted.

Tier 3 targets should attempt to implement as much of the standard libraries as possible and appropriate...

Same as other arm-none-eabi targets.

The target must provide documentation for the Rust community explaining how to build for the target, using cross-compilation if possible.

Same as other arm-none-eabi targets.

Tier 3 targets must not impose burden on the authors of pull requests, or other developers in the community, to maintain the target. In particular, do not post comments (automated or manual) on a PR that derail or suggest a block on the PR based on a tier 3 target. Do not send automated messages or notifications (via any medium, including via @) to a PR author or others involved with a PR regarding a tier 3 target, unless they have opted into such messages.

Noted.

Patches adding or updating tier 3 targets must not break any existing tier 2 or tier 1 target, and must not knowingly break another tier 3 target without approval of either the compiler team or the maintainers of the other tier 3 target.

Noted

Tier 3 targets must be able to produce assembly using at least one of rustc's supported backends from any host target. (Having support in a fork of the backend is not sufficient, it must be upstream.)

Noted

[rustbot]

stdarch is developed in its own repository. If possible, consider making this change to rust-lang/stdarch instead.

cc @Amanieu, @folkertdev, @sayantn

These commits modify compiler targets.
(See the Target Tier Policy.)

Some changes occurred in src/doc/rustc/src/platform-support

cc @Noratrieb

[rustbot]

r? @madsmtm

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[thejpster]

Force pushed with fixed formatting

[madsmtm]

I think the naming is good.

I have reviewed it myself, and would r+, but our policy is that new targets should be approved by a compiler lead, so:

r? compiler_leads

[bors]

☔ The latest upstream changes (presumably #149831) made this pull request unmergeable. Please resolve the merge conflicts.

[taiki-e]

I suspect this can be implemented using thumb interworking. (If so, I'm not sure if LLVM implements it, but I think I can implement it in portable-atomic.)

[thejpster]

What do you suggest I change it to?

[thejpster]

I tried max_atomic_width: Some(32) and even with a relaxed load/store I got:

rust-lld: error: undefined symbol: __sync_val_compare_and_swap_4

So for the same reason as ARMv4T and ARMv5TE I propose just switching atomics off here, and letting portable-atomic provide a work-around if it so chooses.

[taiki-e]

I tried max_atomic_width: Some(32) and even with a relaxed load/store I got:

rust-lld: error: undefined symbol: __sync_val_compare_and_swap_4

So for the same reason as ARMv4T and ARMv5TE I propose just switching atomics off here, and letting portable-atomic provide a work-around if it so chooses.

Thanks for confirming. LLVM just generates __sync_* builtins instead of raising errors (like they do for __yield), so I believe the situation is simpler.

I believe more appropriate approach here is to implement the __sync_* builtins in compiler-builtins with instruction_set(arm::a32) and inline assembly.

[taiki-e]

I believe more appropriate approach here is to implement the __sync_* builtins in compiler-builtins with instruction_set(arm::a32) and inline assembly.

Opened rust-lang/compiler-builtins#1050 which implements this approach.

If you and the compiler-builtins maintainer are okay with that approach, we can set the max-atomic-width to 32 and atomic-cas to true for thumbv6-none-eabi after the new compiler-builtins version containing that change is released.

[rustbot]

This PR was rebased onto a different main commit. Here's a range-diff highlighting what actually changed.

Rebasing is a normal part of keeping PRs up to date, so no action is needed—this note is just to help reviewers.

[thejpster]

Rebased on main and added some updates based on comments above.

[thejpster]

Changes have been proposed to compiler-builtins which rely on this target, so I'm not sure what order we need to merge these PRs.

Maybe merge this where thumbv6 doesn't have CAS, merge the compiler-builtins change, and then update the target to turn CAS on?

@taiki-e would this approach also work for ARMv4T and ARMv5TE (which don't have a DMB equivalent CP15 instruction AFAIK)? Because we turned off all atomics for those recently on the grounds it was completely unclear what the sync* functions would need to do.

[taiki-e]

Changes have been proposed to compiler-builtins which rely on this target, so I'm not sure what order we need to merge these PRs.

Maybe merge this where thumbv6 doesn't have CAS, merge the compiler-builtins change, and then update the target to turn CAS on?

It is easier to understand/use if the target consistently provides atomics regardless of the compiler version, so I was thinking merging the compiler-builtins PR first, then including the update to compiler-builtins containing those changes in this PR. (The compiler-builtins PR uses a custom target to ensure it can build even if this PR hasn't been merged yet.)

@taiki-e would this approach also work for ARMv4T and ARMv5TE (which don't have a DMB equivalent CP15 instruction AFAIK)? Because we turned off all atomics for those recently on the grounds it was completely unclear what the sync* functions would need to do.

That approach does not work with v4t and v5te.

The reason LLVM cannot generate atomic operations for thumbv6-none-eabi is an LLVM issue where it currently doesn't use thumb interworking for atomic lowing. The reason LLVM cannot generate atomic operations for v4t/v5te is because the ISA doesn't have atomic instructions.

	atomic instructions	fence instructions	LLVM generates
v4t/v5te (a32)	load,store,swap	N/A	native load/store instructions (relaxed ordering only) + __sync_* builtins
v4t/v5te (t32)	load,store,swap	N/A	native load/store instructions (relaxed ordering only) + __sync_* builtins
v6k (a32)	load,store,ll/sc,swap(deprecated)	cp15	native atomics instructions
v6k (t32)	load,store,ll/sc(a32 only),swap(deprecated)	cp15(a32 only)	native load/store instructions (relaxed ordering only) + __sync_* builtins
v6t2 (t32)	load,store,ll/sc,swap(deprecated)	cp15	native atomics instructions

Instructions available only in a32 can be invoked using thumb interworking, but it is not possible to perform operations not present in either instruction set.

(The reason v4t/v5te Linux/Android have atomics is that the kernel provides helpers to perform appropriate fallbacks based on the environment, even when atomic instructions are not present in the ISA.)