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    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      BSD 3-Clause "New" or "Revised" License
      6651.7k18634Updated Dec 30, 2024Dec 30, 2024
    • A submodule of Chipyard https://github.com/ucb-bar/chipyard
      HTML
      10931Updated Dec 30, 2024Dec 30, 2024
    • Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.
      C
      42610Updated Dec 30, 2024Dec 30, 2024
    • Scala
      BSD 3-Clause "New" or "Revised" License
      5981154Updated Dec 30, 2024Dec 30, 2024
    • MaDa

      Public
      Verilog
      MIT License
      0000Updated Dec 27, 2024Dec 27, 2024
    • IsaacLab

      Public
      Unified framework for robot learning built on NVIDIA Isaac Sim
      Python
      Other
      1.1k000Updated Dec 27, 2024Dec 27, 2024
    • zephyr

      Public
      Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.
      C
      Apache License 2.0
      6.8k000Updated Dec 26, 2024Dec 26, 2024
    • hammer

      Public
      Hammer: Highly Agile Masks Made Effortlessly from RTL
      Python
      BSD 3-Clause "New" or "Revised" License
      6026020318Updated Dec 26, 2024Dec 26, 2024
    • Chisel RISC-V Vector 1.0 Implementation
      Assembly
      BSD 3-Clause "New" or "Revised" License
      76320Updated Dec 23, 2024Dec 23, 2024
    • C
      BSD 3-Clause "New" or "Revised" License
      13043Updated Dec 23, 2024Dec 23, 2024
    • A submodule of Chipyard https://github.com/ucb-bar/chipyard
      HTML
      10102Updated Dec 21, 2024Dec 21, 2024
    • gemmini

      Public
      Berkeley's Spatial Array Generator
      Scala
      Other
      1778348211Updated Dec 13, 2024Dec 13, 2024
    • pyuartsi

      Public
      A standalone implementation of the Tethered Serial Interface (TSI) in Python.
      Python
      0500Updated Dec 13, 2024Dec 13, 2024
    • SuperNoVA

      Public
      su su su supernova
      C
      BSD 3-Clause "New" or "Revised" License
      0500Updated Dec 13, 2024Dec 13, 2024
    • Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
      C
      Other
      415468Updated Dec 13, 2024Dec 13, 2024
    • ra-isam2

      Public
      Fork of GTSAM. Implements resource-aware ISAM2 for SuperNoVA
      C++
      Other
      0000Updated Dec 12, 2024Dec 12, 2024
    • Collection of device models for spike
      C++
      6713Updated Dec 5, 2024Dec 5, 2024
    • radiance

      Public
      Rocket Chip Generator
      SystemVerilog
      Other
      1.1k100Updated Dec 5, 2024Dec 5, 2024
    • Shell
      BSD 3-Clause "New" or "Revised" License
      7402Updated Dec 2, 2024Dec 2, 2024
    • Symbol and footprint part libraries for KiCad
      0000Updated Nov 27, 2024Nov 27, 2024
    • GNU toolchain for RISC-V, including GCC
      C
      Other
      1.2k000Updated Nov 27, 2024Nov 27, 2024
    • iris-event-utils provides a flexible API for extracting microarchitecture events and data in RTL
      Python
      0100Updated Nov 25, 2024Nov 25, 2024
    • IsaacLabG1Extension

      Public template
      External extenstion template based on Isaac Lab
      Python
      MIT License
      50000Updated Nov 25, 2024Nov 25, 2024
    • A Chisel RTL generator for network-on-chip interconnects
      Scala
      BSD 3-Clause "New" or "Revised" License
      27179193Updated Nov 19, 2024Nov 19, 2024
    • G1-Demos

      Public
      Python
      MIT License
      1100Updated Nov 18, 2024Nov 18, 2024
    • stac-top

      Public
      The SRAM timing analysis chip for verifying SRAMs generated by SRAM22
      Scala
      BSD 3-Clause "New" or "Revised" License
      0400Updated Nov 18, 2024Nov 18, 2024
    • AuRORA

      Public
      Virtualized Accelerator Orchestration for Multi-Tenant Workloads
      C
      1920Updated Nov 17, 2024Nov 17, 2024
    • A SKY 130 tapeout harness built with Chipyard.
      C
      BSD 3-Clause "New" or "Revised" License
      665000Updated Nov 13, 2024Nov 13, 2024
    • SystemVerilog
      BSD 3-Clause "New" or "Revised" License
      1200Updated Nov 13, 2024Nov 13, 2024
    • shuttle

      Public
      A Rocket-based RISC-V superscalar in-order core
      Scala
      22710Updated Oct 29, 2024Oct 29, 2024