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Fix vibrato and envelope bugs (#35)
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* fix vibrato bug

* fix envelope reset on attack

* fix envelope, use proper bit widths
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gtaylormb authored Apr 23, 2024
1 parent e4f33e7 commit 714f983
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Showing 3 changed files with 19 additions and 11 deletions.
14 changes: 7 additions & 7 deletions fpga/modules/operator/src/env_rate_counter.sv
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@
#
#******************************************************************************/
`timescale 1ns / 1ps
`default_nettype none // disable implicit net type declarations
`default_nettype none

module env_rate_counter
import opl3_pkg::*;
Expand All @@ -60,12 +60,12 @@ module env_rate_counter
localparam OVERFLOW_TMP_MAX_VALUE = 7<<15;
localparam PIPELINE_DELAY = 2;

logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp0_p0;
logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp1_p0;
logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_tmp2_p0;
logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] effective_rate_p1 = 0;
logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_value_p1;
logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] requested_rate_shifted_p0;
logic rate_tmp0_p0;
logic [REG_BLOCK_WIDTH+1-1:0] rate_tmp1_p0;
logic [REG_BLOCK_WIDTH+1-1:0] rate_tmp2_p0;
logic [$clog2(60)-1:0] effective_rate_p1 = 0;
logic [$clog2(60)-2-1:0] rate_value_p1;
logic [REG_ENV_WIDTH+2-1:0] requested_rate_shifted_p0;
logic [1:0] rof_p1;
logic [COUNTER_WIDTH-1:0] counter_fifo_out_p1;
logic [COUNTER_WIDTH-1:0] counter_p1;
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14 changes: 11 additions & 3 deletions fpga/modules/operator/src/envelope_generator.sv
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@
#
#******************************************************************************/
`timescale 1ns / 1ps
`default_nettype none // disable implicit net type declarations
`default_nettype none

module envelope_generator
import opl3_pkg::*;
Expand Down Expand Up @@ -168,7 +168,7 @@ module envelope_generator
endcase

if (key_on_pulse_p0)
next_state_p0 = ATTACK;
next_state_p0 = env_int_p0 == 0 ? DECAY : ATTACK;
else if (key_off_pulse_p0)
next_state_p0 = RELEASE;
end
Expand Down Expand Up @@ -211,7 +211,15 @@ module envelope_generator
env_int_p2 <= env_int_p1;

if (sample_clk_en_p[1]) begin
if (state_p1 == ATTACK && rate_counter_overflow_p1 != 0 && env_int_p1 != 0)
if (state_p1 == ATTACK && rate_counter_overflow_p1 != 0)
// The maximum value of overflow is 7. An overflow can only occur
// if m_env < floor(m_env/8)*7 + 1. Let's substitute m_env by 8*x:
// 8*x < 1 + x*7
// <=> 8*x - 7*x < 1
// <=> x < 1
// But the attack only occurs if m_env>0, so an overflow cannot occur
// here.
// +1 for one's complement.
env_int_p2 <= env_int_p1 - (((env_int_p1*rate_counter_overflow_p1) >> 3) + 1);
else if (state_p1 == DECAY || state_p1 == RELEASE) begin
if (env_int_p1 + rate_counter_overflow_p1 > SILENCE)
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2 changes: 1 addition & 1 deletion fpga/modules/top_level/pkg/opl3_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ package opl3_pkg;
localparam OP_OUT_WIDTH = 13;
localparam PHASE_ACC_WIDTH = 20;
localparam AM_VAL_WIDTH = 5;
localparam ENV_RATE_COUNTER_OVERFLOW_WIDTH = 8;
localparam ENV_RATE_COUNTER_OVERFLOW_WIDTH = $clog2(7);

localparam NUM_BANKS = 2;
localparam NUM_OPERATORS_PER_BANK = 18;
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