Fix vibrato, envelope on attack bugs (#34)

* fix vibrato bug * fix envelope reset on attack
gtaylormb · Apr 22, 2024 · e4f33e7 · e4f33e7
1 parent 3463d7a
commit e4f33e7
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Showing 3 changed files with 14 additions and 9 deletions.
diff --git a/fpga/modules/operator/src/env_rate_counter.sv b/fpga/modules/operator/src/env_rate_counter.sv
@@ -53,6 +53,7 @@ module env_rate_counter
     input wire [REG_FNUM_WIDTH-1:0] fnum,
     input wire [REG_BLOCK_WIDTH-1:0] block,
     input wire [REG_ENV_WIDTH-1:0] requested_rate_p0,
+    input wire key_on_pulse_p0,
     output logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow_p1 = 0
 );
     localparam COUNTER_WIDTH = 15;
@@ -66,13 +67,15 @@ module env_rate_counter
     logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_value_p1;
     logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] requested_rate_shifted_p0;
     logic [1:0] rof_p1;
+    logic [COUNTER_WIDTH-1:0] counter_fifo_out_p1;
     logic [COUNTER_WIDTH-1:0] counter_p1;
     logic [COUNTER_WIDTH-1:0] counter_new_p2;
     logic [$clog2(OVERFLOW_TMP_MAX_VALUE)-1:0] overflow_tmp_p1;
     logic [PIPELINE_DELAY:1] requested_rate_not_zero_p;
     logic [PIPELINE_DELAY:1] sample_clk_en_p;
     logic [PIPELINE_DELAY:1] [BANK_NUM_WIDTH-1:0] bank_num_p;
     logic [PIPELINE_DELAY:1] [OP_NUM_WIDTH-1:0] op_num_p;
+    logic key_on_pulse_p1 = 0;
 
     pipeline_sr #(
         .ENDING_CYCLE(PIPELINE_DELAY)
@@ -137,11 +140,17 @@ module env_rate_counter
         .bankb(bank_num),
         .addrb(op_num),
         .dia(counter_new_p2),
-        .dob(counter_p1)
+        .dob(counter_fifo_out_p1)
     );
 
-    always_comb overflow_tmp_p1 = counter_p1 + ((4 | rof_p1) << rate_value_p1);
-    always_comb rate_counter_overflow_p1 = overflow_tmp_p1 >> 15;
+    always_ff @(posedge clk)
+        key_on_pulse_p1 <= key_on_pulse_p0;
+
+    always_comb begin
+        counter_p1 = key_on_pulse_p1 ? 0 : counter_fifo_out_p1;
+        overflow_tmp_p1 = counter_p1 + ((4 | rof_p1) << rate_value_p1);
+        rate_counter_overflow_p1 = overflow_tmp_p1 >> 15;
+    end
 
     always_ff @(posedge clk)
         counter_new_p2 <= overflow_tmp_p1;

diff --git a/fpga/modules/operator/src/envelope_generator.sv b/fpga/modules/operator/src/envelope_generator.sv
@@ -92,7 +92,6 @@ module envelope_generator
     logic [AM_VAL_WIDTH-1:0] am_val_p2;
     logic [REG_ENV_WIDTH-1:0] requested_rate_p0;
     logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow_p1;
-    logic [ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow_p2 = 0;
     logic signed [ENV_WIDTH+1:0] env_tmp_p2; // two more bits wide than env for >, < comparison
     logic [PIPELINE_DELAY:1] sample_clk_en_p;
     logic [PIPELINE_DELAY:1] [BANK_NUM_WIDTH-1:0] bank_num_p;
@@ -208,9 +207,8 @@ module envelope_generator
     );
 
     always_ff @(posedge clk) begin
-        env_int_p1 <= env_int_p0;
+        env_int_p1 <= key_on_pulse_p0 ? SILENCE : env_int_p0;
         env_int_p2 <= env_int_p1;
-        rate_counter_overflow_p2 <= rate_counter_overflow_p1;
 
         if (sample_clk_en_p[1]) begin
             if (state_p1 == ATTACK && rate_counter_overflow_p1 != 0 && env_int_p1 != 0)

diff --git a/fpga/modules/operator/src/vibrato.sv b/fpga/modules/operator/src/vibrato.sv
@@ -47,8 +47,6 @@ module vibrato
 (
     input wire clk,
     input wire sample_clk_en,
-    input wire [BANK_NUM_WIDTH-1:0] bank_num,
-    input wire [OP_NUM_WIDTH-1:0] op_num,
     input wire [REG_FNUM_WIDTH-1:0] fnum,
     input wire dvb,
     output logic signed [REG_FNUM_WIDTH-1:0] vib_val_p2 = 0
@@ -59,7 +57,7 @@ module vibrato
     logic [REG_FNUM_WIDTH-1:0] delta0_p1;
     logic [REG_FNUM_WIDTH-1:0] delta1_p1;
     logic [REG_FNUM_WIDTH-1:0] delta2_p1;
-    logic fnum_p1 = 0;
+    logic [REG_FNUM_WIDTH-1:0] fnum_p1 = 0;
     logic dvb_p1 = 0;
 
     always_ff @(posedge clk) begin