New: Add ASIC synthesis flow, run in CI flow

Change: Add details in the various README

.github/workflows/ci.yaml

@@ -1,13 +1,14 @@
 name: AXI-CROSSBAR
 on: [push]
 jobs:
-  lint-code:
+  Lint:
     runs-on: macos-latest
     steps:
       - uses: actions/checkout@v2
       - run: brew install verilator
+      - run: git submodule update --init --recursive
       - run: ./flow.sh lint
-  sim-tests:
+  Simulation:
     runs-on: macos-latest
     steps:
       - uses: actions/checkout@v2
@@ -17,3 +18,10 @@ jobs:
       - run: verilator -V
       - run: git submodule update --init --recursive
       - run: ./flow.sh sim
+  Synthesis:
+    runs-on: macos-latest
+    steps:
+      - uses: actions/checkout@v2
+      - run: brew install yosys
+      - run: git submodule update --init --recursive
+      - run: ./flow.sh syn

flow.sh

@@ -127,9 +127,15 @@ main() {
 
     if [[ $1 == "syn" ]]; then
         printinfo "Start synthesis flow"
-        cd "$CURDIR/syn"
-        # ./run.sh
-        exit $?
+        cd "$CURDIR/syn/yosys"
+        # AXI4 synthesis
+        ./syn_asic.sh axicb_axi4.ys | tee axi4.log
+        ret=$?
+        # AXI4-lite synthesis
+        ./syn_asic.sh axicb_axi4lite.ys | tee axi4lite.log
+        ret=$((ret+$?))
+        echo "Execution status: $ret"
+        exit $ret
     fi
 }
 

rtl/axicb_crossbar_lite_top.sv

@@ -37,11 +37,6 @@ module axicb_crossbar_lite_top
         parameter MST_PIPELINE = 0,
         parameter SLV_PIPELINE = 0,
 
-        // STRB support:
-        //   - 0: contiguous wstrb (store only 1st/last dataphase)
-        //   - 1: full wstrb transport
-        parameter STRB_MODE = 1,
-
         // USER fields transport enabling (0 deactivate, 1 activate)
         parameter USER_SUPPORT = 0,
         // USER fields width in bits
@@ -505,7 +500,6 @@ module axicb_crossbar_lite_top
     .SLV_NB              (SLV_NB),
     .MST_PIPELINE        (MST_PIPELINE),
     .SLV_PIPELINE        (SLV_PIPELINE),
-    .STRB_MODE           (STRB_MODE),
     .AXI_SIGNALING       (0),
     .USER_SUPPORT        (USER_SUPPORT),
     .AXI_AUSER_W         (AXI_AUSER_W),

syn/yosys/.gitignore

@@ -0,0 +1,3 @@
+*.v
+*.log
+*.history

syn/yosys/README.md

@@ -0,0 +1,14 @@
+# Synthesis
+
+This folder contains basic synthesis scripts using Yosys.
+
+To run them:
+
+```bash
+
+# To run AXI4 crossbar
+./syn_asic.sh axicb_axi4.ys
+
+# To run AXI4-lite crossbar
+./syn_asic.sh axicb_axi4lite.ys
+```

syn/yosys/axicb_axi4.ys

@@ -0,0 +1,35 @@
+# read design modules
+read -incdir ../../rtl
+read -sv2012 ../../rtl/axicb_checker.sv
+read -sv2012 ../../rtl/axicb_crossbar_lite_top.sv
+read -sv2012 ../../rtl/axicb_crossbar_top.sv
+read -sv2012 ../../rtl/axicb_mst_if.sv
+read -sv2012 ../../rtl/axicb_mst_switch.sv
+read -sv2012 ../../rtl/axicb_pipeline.sv
+read -sv2012 ../../rtl/axicb_round_robin.sv
+read -sv2012 ../../rtl/axicb_round_robin_core.sv
+read -sv2012 ../../rtl/axicb_scfifo.sv
+read -sv2012 ../../rtl/axicb_scfifo_ram.sv
+read -sv2012 ../../rtl/axicb_slv_if.sv
+read -sv2012 ../../rtl/axicb_slv_switch.sv
+read -sv2012 ../../rtl/axicb_switch_top.sv
+
+# synthesize the core
+synth -top axicb_crossbar_top
+
+# convert design to (logical) gate-level netlists
+# +/adff2dff.v convert async reset to sync reset, used to mapp FFD correctly
+techmap +/adff2dff.v; opt
+# dffunmap
+
+# map internal register types to the ones from the cell library
+dfflibmap -liberty cmos.lib
+
+# use ABC to map remaining logic to cells from the cell library
+abc -liberty cmos.lib
+
+# cleanup
+clean
+
+# write synthesized design
+write_verilog axicb_crossbar_top.v

syn/yosys/axicb_axi4lite.ys

@@ -0,0 +1,36 @@
+# read design modules
+read -incdir ../../rtl
+
+read -sv2012 ../../rtl/axicb_checker.sv
+read -sv2012 ../../rtl/axicb_crossbar_lite_top.sv
+read -sv2012 ../../rtl/axicb_crossbar_top.sv
+read -sv2012 ../../rtl/axicb_mst_if.sv
+read -sv2012 ../../rtl/axicb_mst_switch.sv
+read -sv2012 ../../rtl/axicb_pipeline.sv
+read -sv2012 ../../rtl/axicb_round_robin.sv
+read -sv2012 ../../rtl/axicb_round_robin_core.sv
+read -sv2012 ../../rtl/axicb_scfifo.sv
+read -sv2012 ../../rtl/axicb_scfifo_ram.sv
+read -sv2012 ../../rtl/axicb_slv_if.sv
+read -sv2012 ../../rtl/axicb_slv_switch.sv
+read -sv2012 ../../rtl/axicb_switch_top.sv
+
+# synthesize the core
+synth -top axicb_crossbar_lite_top
+
+# convert design to (logical) gate-level netlists
+# +/adff2dff.v convert async reset to sync reset, used to mapp FFD correctly
+techmap +/adff2dff.v; opt
+# dffunmap
+
+# map internal register types to the ones from the cell library
+dfflibmap -liberty cmos.lib
+
+# use ABC to map remaining logic to cells from the cell library
+abc -liberty cmos.lib
+
+# cleanup
+clean
+
+# write synthesized design
+write_verilog axicb_crossbar_lite_top.v

syn/yosys/cmos.lib

@@ -0,0 +1,55 @@
+// test comment
+/* test comment */
+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+  cell(DFFSR) {
+    area: 18;
+    ff("IQ", "IQN") { clocked_on: C;
+                  next_state: D;
+                      preset: S;
+                       clear: R; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+    pin(S) { direction: input; }
+    pin(R) { direction: input; }
+    ; // empty statement
+  }
+}

syn/yosys/syn_asic.sh

@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+
+# -e: exit if one command fails
+# -o pipefail: causes a pipeline to fail if any command fails
+set -e -o pipefail
+
+design="./axicb_axi4.ys"
+
+# Check if a design is specified
+if [[ -n $1 ]]; then
+    echo "INFO: will start $1 synthesis"
+    design="$1"
+fi
+
+echo "INFO: Start synthesis flow"
+yosys -V
+
+yosys "$design"
+
+exit 0

test/svut/README.md

@@ -49,20 +49,29 @@ completions. Slave monitor also uses LFSR to handshake with the core.
 
 The drivers can detect the following errors:
 
-- Write outstanding request timeout
-- Read outstanding request timeout
 - AW request timeout
 - W request timeout
 - AR request timeout
+- R completion error
 - BRESP response error
+- BUSER error
+- BID error
 - RRESP response error
+- RUSER error
+- RDATA error
+- RID error
+- RLEN error
 
 The monitors can detect the following errors:
 
-- B response timeout
-- R response timeout
+- B handshake timeout
+- R handshake timeout
 - WDATA error
-- ALEN issue (packet too short or too long)
+- WLEN error
+- ALEN issue
+- AWUSER error
+- ARUSER error
+
 
 ## Execution
 
@@ -76,11 +85,19 @@ To get help and understand all options:
 
 ```bash
 ./run.sh --help
+
+usage: bash ./run.sh ...
+     --tc                (optional)            Path to a testbench setup (located in tb_config)
+-m | --max-traffic       (optional)            Maximun number of requests injected by the drivers
+-t | --timeout           (optional)            Timeout in number of cycles (10000 by default)
+     --no-vcd            (optional)            Don't dump VCD file
+-h | --help                                    Brings up this menu
+
 ```
 To run the complete testsuite:
 
 ```bash
-./run.sh --no-vcd
+./run.sh
 ```
 
 The above command disables VCD dump to avoid dropping an insane number of big
@@ -98,4 +115,4 @@ A subset of the testbench configuration can also be ran:
 ./run.sh --tc tb_config/axi4lite_'*'
 ```
 
-Notice the wildcard if used needs to be quotted.
+(Notice the wildcard if used needs to be quoted)