Fix: Correct clock source for master interface

- top level sourced master interface with slvx_clock instead of aclk - connection fixed - testbench has been changed to better stress clocks, all configuration enabling CDC stages uses now a different clock frequency - outstanding request timeout has been doubled - testbench configurations now specify all clock frequencies Doc: - syntax issue corrected - architecture clock chapter explains when and how enabling CDC stages
dpretet · May 12, 2024 · c9fbc31 · c9fbc31
1 parent d0b8a46
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diff --git a/README.md b/README.md
@@ -47,8 +47,8 @@ Features
 - Master/slave buffering capability, configurable per interface
     - Outstanding request number and payload configurable
     - Seamless support of AXI4 vs AXI4-lite
-- CDC support in master & slave interface. Convert an interface's clock domain
-  from/to the crossbar inner clock domain
+- CDC support in master & slave interface, to convert an agent clock domain
+  from/to the fabric clock domain
 - Round-robin fair-share arbitration
     - Non-blocking arbitration between requesters
     - Priority configurable per master interface
@@ -71,7 +71,7 @@ Features
     - Data width configurable, any width
     - ID width configurable, any width
 - Advanced clock/reset network
-    - Support both aynchronous and synchronous reset schemes
+    - Support both asynchronous and synchronous reset schemes
     - Can handle clock domain crossing if needed, the core being fueled by its
       own clock domain
 - Route read/write requests by address decoding. All slave agents are mapped
@@ -86,8 +86,8 @@ Features
   same AXI ID (!). A master should use different IDs and reorder the completion by itself
 
 Further details can be found in:
-- the architecture [chapter](doc/architecture.md)
-- the IOs/Parameters [chapter](doc/io_parameter.md)
+- The architecture [chapter](doc/architecture.md)
+- The IOs/parameters [chapter](doc/io_parameter.md)
 
 
 ## Verification environment

diff --git a/doc/architecture.md b/doc/architecture.md
@@ -112,6 +112,15 @@ Further details can be found in this
 [excellent document](http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf)
 from the excellent Clifford Cummings.
 
+### Clock Domain Crossing
+
+The core provides a CDC stage for each master or slave interface if needed. The stage is 
+activated with `MSTx_CDC` or `SLVx_CDC`. Internally, the switching fabric uses a specific
+clock (`aclk`) to route the requests and the completions from/to the agents. The master
+and slave interfaces must activate a CDC stage if they don't use the same clock than 
+the fabric (same frequency & phase). If an agent uses the same clock than the fabric, the 
+agent must also use the same reset to ensure a clean reset sequence.
+
 
 ## AXI4 / AXI4-lite support
 

diff --git a/flow.sh b/flow.sh
@@ -118,7 +118,7 @@ main() {
 
     if [[ $1 == "sim" ]]; then
         source script/setup.sh
-        cd $CURDIR/test/svut
+        cd "$CURDIR/test/svut"
         ./run.sh --no-debug-log --no-vcd
         ret=$?
         echo "Execution status: $ret"

diff --git a/rtl/axicb_crossbar_top.sv b/rtl/axicb_crossbar_top.sv
@@ -37,11 +37,6 @@ module axicb_crossbar_top
         parameter MST_PIPELINE = 0,
         parameter SLV_PIPELINE = 0,
 
-        // STRB support:
-        //   - 0: contiguous wstrb (store only 1st/last dataphase)
-        //   - 1: full wstrb transport
-        parameter STRB_MODE = 1,
-
         // AXI Signals Supported:
         //   - 0: AXI4-lite
         //   - 1: AXI
@@ -82,9 +77,9 @@ module axicb_crossbar_top
         //                    determine which master to route back the
         //                    BRESP/RRESP completions.
         //
-        //   - MSTx_RW: Slect if the interface is 
+        //   - MSTx_RW: Slect if the interface is
         //         - Read/Write (=0)
-        //         - Read-only (=1) 
+        //         - Read-only (=1)
         //         - Write-only (=2)
         //
         // The size of a master's internal buffer is equal to:
@@ -759,7 +754,6 @@ module axicb_crossbar_top
     .AXI_ID_W          (AXI_ID_W),
     .AXI_DATA_W        (AXI_DATA_W),
     .SLV_NB            (SLV_NB),
-    .STRB_MODE         (STRB_MODE),
     .AXI_SIGNALING     (AXI_SIGNALING),
     .MST_CDC           (MST0_CDC),
     .MST_OSTDREQ_NUM   (MST0_OSTDREQ_NUM),
@@ -856,7 +850,6 @@ module axicb_crossbar_top
     .AXI_ID_W          (AXI_ID_W),
     .AXI_DATA_W        (AXI_DATA_W),
     .SLV_NB            (SLV_NB),
-    .STRB_MODE         (STRB_MODE),
     .AXI_SIGNALING     (AXI_SIGNALING),
     .MST_CDC           (MST1_CDC),
     .MST_OSTDREQ_NUM   (MST1_OSTDREQ_NUM),
@@ -953,7 +946,6 @@ module axicb_crossbar_top
     .AXI_ID_W          (AXI_ID_W),
     .AXI_DATA_W        (AXI_DATA_W),
     .SLV_NB            (SLV_NB),
-    .STRB_MODE         (STRB_MODE),
     .AXI_SIGNALING     (AXI_SIGNALING),
     .MST_CDC           (MST2_CDC),
     .MST_OSTDREQ_NUM   (MST2_OSTDREQ_NUM),
@@ -1050,7 +1042,6 @@ module axicb_crossbar_top
     .AXI_ID_W          (AXI_ID_W),
     .AXI_DATA_W        (AXI_DATA_W),
     .SLV_NB            (SLV_NB),
-    .STRB_MODE         (STRB_MODE),
     .AXI_SIGNALING     (AXI_SIGNALING),
     .MST_CDC           (MST3_CDC),
     .MST_OSTDREQ_NUM   (MST3_OSTDREQ_NUM),
@@ -1226,7 +1217,6 @@ module axicb_crossbar_top
     .AXI_ADDR_W       (AXI_ADDR_W),
     .AXI_ID_W         (AXI_ID_W),
     .AXI_DATA_W       (AXI_DATA_W),
-    .STRB_MODE        (STRB_MODE),
     .AXI_SIGNALING    (AXI_SIGNALING),
     .SLV_CDC          (SLV0_CDC),
     .SLV_OSTDREQ_NUM  (SLV0_OSTDREQ_NUM),
@@ -1246,9 +1236,9 @@ module axicb_crossbar_top
     )
     mst0_if
     (
-    .i_aclk       (slv0_aclk),
-    .i_aresetn    (slv0_aresetn),
-    .i_srst       (slv0_srst),
+    .i_aclk       (aclk),
+    .i_aresetn    (aresetn),
+    .i_srst       (srst),
     .i_awvalid    (o_awvalid[0]),
     .i_awready    (o_awready[0]),
     .i_awch       (o_awch[0*AWCH_W+:AWCH_W]),
@@ -1324,7 +1314,6 @@ module axicb_crossbar_top
     .AXI_ADDR_W       (AXI_ADDR_W),
     .AXI_ID_W         (AXI_ID_W),
     .AXI_DATA_W       (AXI_DATA_W),
-    .STRB_MODE        (STRB_MODE),
     .AXI_SIGNALING    (AXI_SIGNALING),
     .SLV_CDC          (SLV1_CDC),
     .SLV_OSTDREQ_NUM  (SLV1_OSTDREQ_NUM),
@@ -1344,9 +1333,9 @@ module axicb_crossbar_top
     )
     mst1_if
     (
-    .i_aclk       (slv1_aclk),
-    .i_aresetn    (slv1_aresetn),
-    .i_srst       (slv1_srst),
+    .i_aclk       (aclk),
+    .i_aresetn    (aresetn),
+    .i_srst       (srst),
     .i_awvalid    (o_awvalid[1]),
     .i_awready    (o_awready[1]),
     .i_awch       (o_awch[1*AWCH_W+:AWCH_W]),
@@ -1422,7 +1411,6 @@ module axicb_crossbar_top
     .AXI_ADDR_W       (AXI_ADDR_W),
     .AXI_ID_W         (AXI_ID_W),
     .AXI_DATA_W       (AXI_DATA_W),
-    .STRB_MODE        (STRB_MODE),
     .AXI_SIGNALING    (AXI_SIGNALING),
     .SLV_CDC          (SLV2_CDC),
     .SLV_OSTDREQ_NUM  (SLV2_OSTDREQ_NUM),
@@ -1442,9 +1430,9 @@ module axicb_crossbar_top
     )
     mst2_if
     (
-    .i_aclk       (slv2_aclk),
-    .i_aresetn    (slv2_aresetn),
-    .i_srst       (slv2_srst),
+    .i_aclk       (aclk),
+    .i_aresetn    (aresetn),
+    .i_srst       (srst),
     .i_awvalid    (o_awvalid[2]),
     .i_awready    (o_awready[2]),
     .i_awch       (o_awch[2*AWCH_W+:AWCH_W]),
@@ -1520,7 +1508,6 @@ module axicb_crossbar_top
     .AXI_ADDR_W       (AXI_ADDR_W),
     .AXI_ID_W         (AXI_ID_W),
     .AXI_DATA_W       (AXI_DATA_W),
-    .STRB_MODE        (STRB_MODE),
     .AXI_SIGNALING    (AXI_SIGNALING),
     .SLV_CDC          (SLV3_CDC),
     .SLV_OSTDREQ_NUM  (SLV3_OSTDREQ_NUM),
@@ -1540,9 +1527,9 @@ module axicb_crossbar_top
     )
     mst3_if
     (
-    .i_aclk       (slv3_aclk),
-    .i_aresetn    (slv3_aresetn),
-    .i_srst       (slv3_srst),
+    .i_aclk       (aclk),
+    .i_aresetn    (aresetn),
+    .i_srst       (srst),
     .i_awvalid    (o_awvalid[3]),
     .i_awready    (o_awready[3]),
     .i_awch       (o_awch[3*AWCH_W+:AWCH_W]),
@@ -1610,5 +1597,4 @@ module axicb_crossbar_top
     );
 
 endmodule
-
 `resetall
diff --git a/rtl/axicb_mst_if.sv b/rtl/axicb_mst_if.sv
@@ -14,14 +14,9 @@ module axicb_mst_if
         // Data width in bits
         parameter AXI_DATA_W = 8,
 
-        // STRB support:
-        //   - 0: contiguous wstrb (store only 1st/last dataphase)
-        //   - 1: full wstrb transport
-        parameter STRB_MODE = 1,
-
         // AXI Signals Supported:
         //   - 0: AXI4-lite
-        //   - 2: AXI4
+        //   - 1: AXI4
         parameter AXI_SIGNALING = 0,
 
         // Keep aboslute address in crossbar memory map

diff --git a/rtl/axicb_slv_if.sv b/rtl/axicb_slv_if.sv
@@ -17,11 +17,6 @@ module axicb_slv_if
         // Number of slave
         parameter SLV_NB = 4,
 
-        // STRB support:
-        //   - 0: contiguous wstrb (store only 1st/last dataphase)
-        //   - 1: full wstrb transport
-        parameter STRB_MODE = 1,
-
         // AXI Signals Supported:
         //   - 0: AXI4-lite
         //   - 1: AXI4

diff --git a/rtl/axicb_switch_top.sv b/rtl/axicb_switch_top.sv
@@ -550,6 +550,5 @@ module axicb_switch_top
     end
     endgenerate
 
-    endmodule
-
-    `resetall
+endmodule
+`resetall
diff --git a/test/svut/README.md b/test/svut/README.md
@@ -13,7 +13,6 @@ following setup:
 
 - 4 masters
 - 4 slaves
-- Use a full-mode STRB
 - All masters have the same priority in arbitration stages
 - All masters can access the four slaves
 

diff --git a/test/svut/src/axicb_crossbar_top_testbench.sv b/test/svut/src/axicb_crossbar_top_testbench.sv
@@ -29,7 +29,6 @@ module axicb_crossbar_top_testbench();
     parameter SLV_NB = 4;
     parameter MST_PIPELINE = `MST_PIPELINE;
     parameter SLV_PIPELINE = `SLV_PIPELINE;
-    parameter STRB_MODE = 1;
     parameter AXI_SIGNALING = `AXI_SIGNALING;
     parameter USER_SUPPORT = `USER_SUPPORT;
     parameter AXI_AUSER_W = 4;
@@ -489,7 +488,6 @@ module axicb_crossbar_top_testbench();
     .SLV_NB                 (SLV_NB),
     .MST_PIPELINE           (MST_PIPELINE),
     .SLV_PIPELINE           (SLV_PIPELINE),
-    .STRB_MODE              (STRB_MODE),
     .AXI_SIGNALING          (AXI_SIGNALING),
     .USER_SUPPORT           (USER_SUPPORT),
     .AXI_AUSER_W            (AXI_AUSER_W),
@@ -1548,15 +1546,15 @@ module axicb_crossbar_top_testbench();
     initial slv2_aclk = 0;
     initial slv3_aclk = 0;
 
-    always #2 aclk = ~aclk;
-    always #2 mst0_aclk = ~mst0_aclk;
-    always #2 mst1_aclk = ~mst1_aclk;
-    always #2 mst2_aclk = ~mst2_aclk;
-    always #2 mst3_aclk = ~mst3_aclk;
-    always #2 slv0_aclk = ~slv0_aclk;
-    always #2 slv1_aclk = ~slv1_aclk;
-    always #2 slv2_aclk = ~slv2_aclk;
-    always #2 slv3_aclk = ~slv3_aclk;
+    always #`FAB_CLK aclk = !aclk;
+    always #`MST0_CLK mst0_aclk = !mst0_aclk;
+    always #`MST1_CLK mst1_aclk = !mst1_aclk;
+    always #`MST2_CLK mst2_aclk = !mst2_aclk;
+    always #`MST3_CLK mst3_aclk = !mst3_aclk;
+    always #`SLV0_CLK slv0_aclk = !slv0_aclk;
+    always #`SLV1_CLK slv1_aclk = !slv1_aclk;
+    always #`SLV2_CLK slv2_aclk = !slv2_aclk;
+    always #`SLV3_CLK slv3_aclk = !slv3_aclk;
 
     `ifndef NOVCD
     // To dump data for visualization:

diff --git a/test/svut/src/functions.sh b/test/svut/src/functions.sh
@@ -47,7 +47,6 @@ check_status() {
 # Grab arguments and values
 #------------------------------------------------------------------------------
 get_args() {
-    # First handle the arguments
     while [ "$1" != "" ]; do
         case $1 in
             -m | --max-traffic )
@@ -63,11 +62,9 @@ get_args() {
                 TIMEOUT=$1
             ;;
             --no-vcd )
-                shift
                 NOVCD=1
             ;;
             --no-debug-log )
-                shift
                 NODEBUG=1
             ;;
             -h | --help )

diff --git a/test/svut/tb_config/axi4_+cdc_+or_-priority_+pipe_-route.cfg b/test/svut/tb_config/axi4_+cdc_+or_-priority_+pipe_-route.cfg
@@ -1,19 +1,19 @@
-OR_TIMEOUT,5000
+OR_TIMEOUT,10000
 AXI_ADDR_W,16
 AXI_ID_W,8
 AXI_DATA_W,32
 MST_PIPELINE,1
-SLV_PIPELINE,2
+SLV_PIPELINE,1
 AXI_SIGNALING,1
 USER_SUPPORT,1
-MST0_CDC,0
+MST0_CDC,1
 MST1_CDC,1
-MST2_CDC,0
+MST2_CDC,1
 MST3_CDC,1
-SLV0_CDC,0
+SLV0_CDC,1
 SLV1_CDC,1
 SLV2_CDC,1
-SLV3_CDC,0
+SLV3_CDC,1
 MST0_OSTDREQ_NUM,1
 MST0_OSTDREQ_SIZE,1
 MST0_PRIORITY,0
@@ -46,3 +46,12 @@ MST0_ROUTES,15
 MST1_ROUTES,15
 MST2_ROUTES,15
 MST3_ROUTES,15
+MST0_CLK,1
+MST1_CLK,3
+MST2_CLK,5
+MST3_CLK,4
+FAB_CLK,1
+SLV0_CLK,2
+SLV1_CLK,4
+SLV2_CLK,3
+SLV3_CLK,5
diff --git a/test/svut/tb_config/axi4_+cdc_+or_-priority_-pipe_-route.cfg b/test/svut/tb_config/axi4_+cdc_+or_-priority_-pipe_-route.cfg
@@ -1,19 +1,19 @@
-OR_TIMEOUT,5000
+OR_TIMEOUT,10000
 AXI_ADDR_W,16
 AXI_ID_W,8
 AXI_DATA_W,32
 MST_PIPELINE,0
 SLV_PIPELINE,0
 AXI_SIGNALING,1
 USER_SUPPORT,0
-MST0_CDC,0
+MST0_CDC,1
 MST1_CDC,1
-MST2_CDC,0
+MST2_CDC,1
 MST3_CDC,1
-SLV0_CDC,0
+SLV0_CDC,1
 SLV1_CDC,1
 SLV2_CDC,1
-SLV3_CDC,0
+SLV3_CDC,1
 MST0_OSTDREQ_NUM,1
 MST0_OSTDREQ_SIZE,1
 MST0_PRIORITY,0
@@ -46,3 +46,12 @@ MST0_ROUTES,15
 MST1_ROUTES,15
 MST2_ROUTES,15
 MST3_ROUTES,15
+MST0_CLK,1
+MST1_CLK,3
+MST2_CLK,5
+MST3_CLK,4
+FAB_CLK,1
+SLV0_CLK,2
+SLV1_CLK,4
+SLV2_CLK,3
+SLV3_CLK,5