introduce verilog_sva_property_typet
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IEEE 1800-2017 16.6 Boolean expressions introduces rules on how to convert Boolean expressions into SVA sequences or properties. This introduces an expression for this conversion.
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This introduces a type for Verilog SVA properties to distinguish properties from state predicates and sequences.
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This introduces a type for Verilog SVA properties to distinguish properties from state predicates and sequences.