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introduce verilog_sva_property_typet
This introduces a type for Verilog SVA properties to distinguish properties from state predicates and sequences.
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8 files changed

+142
-79
lines changed

8 files changed

+142
-79
lines changed

src/hw_cbmc_irep_ids.h

+1
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,7 @@ IREP_ID_ONE(verilog_null)
140140
IREP_ID_ONE(verilog_event)
141141
IREP_ID_ONE(verilog_event_trigger)
142142
IREP_ID_ONE(verilog_string)
143+
IREP_ID_ONE(verilog_sva_property)
143144
IREP_ID_ONE(verilog_sva_sequence)
144145
IREP_ID_ONE(reg)
145146
IREP_ID_ONE(macromodule)

src/temporal-logic/normalize_property.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ exprt normalize_property(exprt expr)
105105
{
106106
// top-level only
107107
if(expr.id() == ID_sva_cover)
108-
expr = sva_always_exprt{not_exprt{to_sva_cover_expr(expr).op()}};
108+
expr = sva_always_exprt{sva_not_exprt{to_sva_cover_expr(expr).op()}};
109109

110110
expr = trivial_sva(expr);
111111

src/temporal-logic/trivial_sva.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ exprt trivial_sva(exprt expr)
8484
}
8585
else if(expr.id() == ID_sva_not)
8686
{
87-
// Same as regular 'not'. These do not apply to sequences.
87+
// Same as boolean 'not'. These do not apply to sequences.
8888
expr = not_exprt{to_sva_not_expr(expr).op()};
8989
}
9090
else if(expr.id() == ID_sva_if)

src/trans-word-level/property.cpp

+5-4
Original file line numberDiff line numberDiff line change
@@ -537,10 +537,10 @@ static obligationst property_obligations_rec(
537537
return property_obligations_rec(
538538
to_typecast_expr(property_expr).op(), current, no_timeframes);
539539
}
540-
else if(property_expr.id() == ID_not)
540+
else if(property_expr.id() == ID_sva_not)
541541
{
542542
// We need NNF, try to eliminate the negation.
543-
auto &op = to_not_expr(property_expr).op();
543+
auto &op = to_sva_not_expr(property_expr).op();
544544

545545
auto op_negated_opt = negate_property_node(op);
546546

@@ -576,8 +576,9 @@ static obligationst property_obligations_rec(
576576
else
577577
{
578578
// state formula
579-
return obligationst{
580-
instantiate_property(property_expr, current, no_timeframes)};
579+
auto sampled =
580+
instantiate_property(not_exprt{op}, current, no_timeframes);
581+
return obligationst{sampled};
581582
}
582583
}
583584
else if(property_expr.id() == ID_sva_implies)

src/verilog/sva_expr.cpp

+3-1
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,9 @@ exprt sva_sequence_repetition_star_exprt::lower() const
118118
{
119119
auto n_expr = from_integer(n, integer_typet{});
120120
result = sva_or_exprt{
121-
std::move(result), sva_sequence_repetition_star_exprt{op(), n_expr}};
121+
std::move(result),
122+
sva_sequence_repetition_star_exprt{op(), n_expr},
123+
verilog_sva_sequence_typet{}};
122124
}
123125

124126
return result;

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