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QtRvSim version 0.9.6 release
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@ppisa ppisa released this 13 Dec 13:03
· 84 commits to master since this release
v0.9.6
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ppisa Pavel Pisa
GPG key ID: 868410FF2B4709CB
Learn about vigilant mode.
ed7eafa
  • GUI: add reset widows menu entry to restore default windows layout
  • Machine: extend CSR support to pass rv32mi-p-mcsr and rv64mi-p-mcsr official test
  • Machine: serial port interrupts reworked for RISC-V as platform irq 16 and 17
  • GUI: RISC-V ACLINT MTIMER mapping added into resources/samples/template.S
  • Machine: implemented RISC-V A extension for RV32IMA/RV64IMA support
  • GUI: the XLEN, atomic and multiply options available in new simulation dialog
  • GUI: update registers and CSR views for bare RV64IMA support
  • Machine and GUI: simple level 2 cache implementation
  • GUI: increase cache set count limit to 1024
  • CLI: add isa-variant, cycle-limit and l2-cache options
  • CLI: dump-ranges allows to use symbols even from internal assembly
  • Memory: correctly propagate external/DMA changes to GUI
  • Machine: where possible, re-implement pseudo instructions by aliase tables
  • os_emulation: resolve problem with write and read from/to stack area on RV32
  • GUI: fix double free of children widgets in control register widget
  • GUI: refactor gui source file to tree structure
  • GUI: program view - collapse address and breakpoint if space is limited
  • GUI: split central widget tabs to coreview and editor
  • GUI: editor line numbers and highlight error in the editor on message click
  • GUI: editor toggle comment (ctrl+/)
  • GUI: ensure that all lines of external make process output are processed
  • os_emulation: correct ftruncate syscall arguments for 64 and 32-bit ABI
  • Update README.md to document interrupt, trap, ACLINT+MTIMER and AMO support
  • CI: drop support for Ubuntu 18
  • Project: bump to c++17
  • Students work was funded by RPAPS 2023 initiative at Czech Technical University in Prague Faculty of Electrical Engineering, https://fel.cvut.cz/
  • We thanks for actual funding to Czech Technical University https://www.cvut.cz/

For Ubuntu use https://launchpad.net/~qtrvsimteam/+archive/ubuntu/ppa
For SUSE, Fedora and Debian https://software.opensuse.org/download.html?project=home%3Ajdupak&package=qtrvsim
For Arch https://aur.archlinux.org/pkgbase/qtrvsim
WebAssembly online version https://comparch.edu.cvut.cz/qtrvsim/app

QtRvSim articles, presentations and their recordings as well as more about Computer Architectures courses at the Czech Technical University in Prague are presented at https://comparch.edu.cvut.cz/

The project has been presented on FOSDEM 2023, presentation and recordings are available

The educational VHDL RISC-V core modeled according to the QtRvSim (single cycle and 5-stage pipeline) has been designed by Damir Gruncl for the CTU FEE Advanced Computer Architectures course https://gitlab.fel.cvut.cz/b4m35pap/rvapo-vhdl and tested in GHDL simulation and on Zilinx Zynq and iCE-40 FPGA targets

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