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Instantiations Wrapped with One Port #1889

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bkueffle opened this issue Apr 24, 2023 · 2 comments · May be fixed by #1909
Open

Instantiations Wrapped with One Port #1889

bkueffle opened this issue Apr 24, 2023 · 2 comments · May be fixed by #1909
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@jbylicki
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formatter Verilog code formatter issues

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@bkueffle
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Behavior around module instantiation wrapping doesn't seem desirable. Whenever only one port and/or parameter is given, the instantiation is done on one line (as long as it fits on the line). If 2 ports or 2 parameters are given, then the instantiation style is wrapped, even if it does fit on one line.

Test case

  module_name #(
      .Param1(Param1)
  ) only_one_param_or_port (
      .port_i(a_i)
  );

  module_name #(
      .Param1(Param1),
      .Param2(Param2)
  ) two_or_more_param_or_ports (
      .port_i(a_i)
  );

  module_name fits_on_one_line (
      .port_i(a_i),
      .port_o(b_o)
  );

Actual output

  module_name #(.Param1(Param1)) only_one_param_or_port (.port_i(a_i));

  module_name #(
      .Param1(Param1),
      .Param2(Param2)
  ) two_or_more_param_or_ports (
      .port_i(a_i)
  );

  module_name fits_on_one_line (
      .port_i(a_i),
      .port_o(b_o)
  );

Include any possible diagnostic messages from the formatter.

The output I desire

I always want to wrap my instantiations, even if it fits on one line.

  module_name #(
      .Param1(Param1)
  ) only_one_param_or_port (
      .port_i(a_i)
  );

  module_name #(
      .Param1(Param1),
      .Param2(Param2)
  ) two_or_more_param_or_ports (
      .port_i(a_i)
  );

  module_name fits_on_one_line (
      .port_i(a_i),
      .port_o(b_o)
  );

Another Output Option that Some May Prefer

Some may prefer making the instantiation fit on one line if it is <= the character limit.

  module_name fits_on_one_line (.port_i(a_i), .port_o(b_o));
@bkueffle bkueffle added the formatter Verilog code formatter issues label Apr 24, 2023
@hzeller
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hzeller commented Apr 24, 2023

Thanks for the report. Yes indeed, these things should be more configurable. So three choices would be good: multi-line always, single-line iff one parameter, single-line if all parameters fit within line length.

@jbylicki Since you're on a roll currently with formatter updates, is this something that interests you ?

@bkueffle
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Yeah to prevent bloat I think just two options would suffice:

Multi-line always.
Single-line if all parameters & ports fit within line length.

single-line iff one parameter and/or port seems like a bug/side effect of some other rule. I don't know any style that would use this.

@tgorochowik tgorochowik moved this to v1.1 - features in Verible - release planning Apr 25, 2023
@jbylicki jbylicki linked a pull request May 5, 2023 that will close this issue
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@jbylicki jbylicki

Labels
formatter Verilog code formatter issues
Projects
Verible - release planning
Status: v1.1 - features
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Successfully merging a pull request may close this issue.

Added an always_wrap_module_instantiations flag antmicro/verible
3 participants
@hzeller @bkueffle @jbylicki