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Issues: chipsalliance/treadle
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More than two clocks at top level of dut issues warning
bug
Something isn't working
#358
opened Sep 10, 2021 by
chick
Make it possible to create a TreadleTester without running firrtl optimizations
#352
opened Aug 23, 2021 by
ekiwi
Provide a convenience method to launch treadle REPL on a chisel design
#242
opened Aug 12, 2020 by
chick
Build Scala black boxes to match rocket-chip verilog black boxes
enhancement
New feature or request
#148
opened Nov 5, 2019 by
chick
[RFC] Allow users to create Scala versions of any firrtl module
enhancement
New feature or request
#68
opened Dec 4, 2018 by
chick
Add Support for [Sparse] Mems larger than 2^31 - 1 (ie. BigInt address)
#51
opened Jul 17, 2018 by
jackkoenig
ProTip!
Follow long discussions with comments:>50.