Chisel v7.1.0

Features

• [core] Add Temporal inline layer, trait (by @seldridge in #5018)
• [core] Add LayerControl.Disable (by @seldridge in #5019)
• [chiselsim] Drop Temporal layers for Verilator Cli (by @seldridge in #5024)

Fixes

• Fix construction of PseudoModules to have correct parent (by @jackkoenig in #5012)
  This fixes subtle bugs where accessing children of an Instance (whether directly or by using Select APIs) could change the result of future Select to be incorrect. For example, a call to Select.unsafe.allCurrentInstancesIn could cause Select.unsafe.currentInstancesIn to also incorrectly include grandchildren and all other transitive children.
• [svsim] Update c++ CFLAGS for verilator from c++14 to c++17 (by @Gallagator in #5017)
  Verilator CFLAGS bumped from c++14 to c++17
• Overload Stage methods to use Seq[Annotation] (by @jackkoenig in #5030)
  Also deprecate the older forms using AnnotationSeq.

Documentation

• [docs] Update layer docs for temporal layer, NFC (by @seldridge in #5020)
• [docs] Fix duplicate versions in Firrtl Version table (by @jackkoenig in #5025)
  Also refactor some build util code to be Tasks so they can be cached on disk.
• [doc] Document temporal layers and ChiselSim (by @seldridge in #5027)

Dependency Updates

• [cd] Bump CIRCT from firtool-1.128.0 to firtool-1.129.0 (by @chiselbot in #5010)
• [cd] Bump CIRCT from firtool-1.129.0 to firtool-1.130.0 (by @chiselbot in #5015)
• [cd] Bump CIRCT from firtool-1.130.0 to firtool-1.131.0 (by @chiselbot in #5021)

Build and Internal Changes

• Restore binary compatibility checking (by @jackkoenig in #5028)

Full Changelog: v7.0.0...v7.1.0