arch/arm/stm32l5: enable LPUART1 console on ST-Link VCP. on nucleo-l552ze board#18526
Merged
xiaoxiang781216 merged 1 commit intoapache:masterfrom Mar 11, 2026
Merged
Conversation
051c55d to
12b14f7
Compare
jerpelea
previously approved these changes
Mar 11, 2026
xiaoxiang781216
previously approved these changes
Mar 11, 2026
Three fixes to make LPUART1 work as NSH console on Nucleo-L552ZE-Q: 1. stm32l5_lowputc: add LPUART-specific BRR formula (256 * fCK / baud) instead of reusing the standard USART divisor calculation. 2. stm32_boot: enable VDDIO2 and reconfigure LPUART1 GPIOs (PG7/PG8) in board_initialize. The low-level setup runs before VDDIO2 is enabled, so GPIOG writes silently fail. 3. stm32l5_serial: fix LPUART1 apbclock (PCLK1 not PCLK2), add LPUART BRR branch in setformat, cast to uint64_t to prevent 32-bit overflow in (fCK << 8). Also switch nsh defconfig from USART3 to LPUART1, add GPIO_LPUART1 pin definitions in board.h, and update board documentation. Signed-off-by: anjiahao <anjiahao@xiaomi.com>
1bb8dfd
12b14f7 to
1bb8dfd
Compare
anchao
approved these changes
Mar 11, 2026
simbit18
approved these changes
Mar 11, 2026
xiaoxiang781216
approved these changes
Mar 11, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
BRR = 256 * fCK / baudinstead of the standard USART divisor.stm32l5_lowsetup()runs before VDDIO2 is enabled, so GPIOG writes silently fail. Added VDDIO2 enable and GPIO reconfiguration instm32l5_board_initialize().apbclockwas incorrectly set to PCLK2 (should be PCLK1 per RCC_APB1ENR2), and the runtimesetformat()lacked an LPUART BRR branch. Also cast touint64_tto prevent 32-bit overflow in(fCK << 8).Impact
Testing
I confirm that changes are verified on local setup and works as intended:
Testing logs before change:
Testing logs after change:
Verified via GDB/OpenOCD register inspection:
PR verification Self-Check