Fixed mlp_int8 design to only add portal module for multi-rad designs

andrewboutros · Sep 30, 2024 · ad6c35f · ad6c35f
1 parent 8734eac
commit ad6c35f
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Showing 6 changed files with 25 additions and 21 deletions.
diff --git a/rad-sim/example-designs/mlp_int8/compiler/gen_testcase.py b/rad-sim/example-designs/mlp_int8/compiler/gen_testcase.py
@@ -76,8 +76,10 @@
 idx = idx + 1
 clocks_file.write('inst_loader 0 0\n')
 
-placement_file.write('portal_inst 0 16 axis\n')
-clocks_file.write('portal_inst 0 0\n')
+#WARNING: uncomment out if multi-rad design
+print('WARNING: if multi-rad mlp_int8 design, uncomment out lines 81-82 of gen_testcase.py')
+# placement_file.write('portal_inst 0 16 axis\n')
+# clocks_file.write('portal_inst 0 0\n')
 
 placement_file.close()
 clocks_file.close()

diff --git a/rad-sim/example-designs/mlp_int8/config.yml b/rad-sim/example-designs/mlp_int8/config.yml
@@ -4,7 +4,7 @@ noc:
   clk_period: [1.0]
   payload_width: [166]
   topology: ['mesh']
-  dim_x: [5]
+  dim_x: [4]
   dim_y: [4] 
   routing_func: ['dim_order']
   vcs: [5]

diff --git a/rad-sim/example-designs/mlp_int8/mlp.clks b/rad-sim/example-designs/mlp_int8/mlp.clks
@@ -14,4 +14,3 @@ input_dispatcher2 0 0
 output_collector 0 0
 weight_loader 0 0
 inst_loader 0 0
-portal_inst 0 0
diff --git a/rad-sim/example-designs/mlp_int8/mlp.place b/rad-sim/example-designs/mlp_int8/mlp.place
@@ -1,17 +1,16 @@
-layer0_mvm0 0 12 axis
-layer0_mvm1 0 7 axis
-layer0_mvm2 0 8 axis
-layer1_mvm0 0 6 axis
-layer1_mvm1 0 15 axis
-layer1_mvm2 0 11 axis
-layer2_mvm0 0 3 axis
-layer2_mvm1 0 10 axis
-layer3_mvm0 0 1 axis
-layer3_mvm1 0 0 axis
-input_dispatcher0 0 5 axis
-input_dispatcher1 0 9 axis
-input_dispatcher2 0 2 axis
-output_collector 0 13 axis
-weight_loader 0 4 axis
-inst_loader 0 14 axis
-portal_inst 0 16 axis
+layer0_mvm0 0 13 axis
+layer0_mvm1 0 6 axis
+layer0_mvm2 0 1 axis
+layer1_mvm0 0 2 axis
+layer1_mvm1 0 14 axis
+layer1_mvm2 0 0 axis
+layer2_mvm0 0 9 axis
+layer2_mvm1 0 3 axis
+layer3_mvm0 0 4 axis
+layer3_mvm1 0 12 axis
+input_dispatcher0 0 15 axis
+input_dispatcher1 0 11 axis
+input_dispatcher2 0 7 axis
+output_collector 0 5 axis
+weight_loader 0 10 axis
+inst_loader 0 8 axis
diff --git a/rad-sim/example-designs/mlp_int8/mlp_top.cpp b/rad-sim/example-designs/mlp_int8/mlp_top.cpp
@@ -117,7 +117,9 @@ mlp_top::mlp_top(const sc_module_name &name, RADSimDesignContext* radsim_design)
   iloader->mvm_id_fifo_wen(inst_loader_mvm_id_fifo_wen);
   iloader->mvm_id_fifo_wdata(inst_loader_mvm_id_fifo_wdata);
 
+  #ifndef SINGLE_RAD
   this->portal_inst->rst(rst);
+  #endif
   radsim_design->BuildDesignContext("mlp.place", "mlp.clks");
   radsim_design->CreateSystemNoCs(rst);
   radsim_design->ConnectModulesToNoC();

diff --git a/rad-sim/example-designs/npu/npu_top.cpp b/rad-sim/example-designs/npu/npu_top.cpp
@@ -80,7 +80,9 @@ npu_top::npu_top(const sc_module_name &name, RADSimDesignContext* radsim_design)
     vector_elementwise_blocks[thread_id]->ext_output_fifo_rdata(ofifo_rdata[thread_id]);
   }                                                             
 
+  #ifndef SINGLE_RAD
   this->portal_inst->rst(rst);
+  #endif
   radsim_design->BuildDesignContext("npu.place", "npu.clks");
   radsim_design->CreateSystemNoCs(rst);
   radsim_design->ConnectModulesToNoC();