Merge pull request #11 from andrewboutros/dev-gtrieu

RTL Add Example (PR into main)

rad-sim/example-designs/rtl_add/CMakeLists.txt

@@ -0,0 +1,35 @@
+cmake_minimum_required(VERSION 3.19)
+find_package(SystemCLanguage CONFIG REQUIRED)
+
+add_subdirectory(modules/rtl)
+
+include_directories(
+  ./
+  modules
+  ../../sim
+  ../../sim/noc
+  ../../sim/noc/booksim
+  ../../sim/noc/booksim/networks
+  ../../sim/noc/booksim/routers
+)
+
+set(srcfiles
+  modules/adder_wrapper.cpp
+  modules/client_wrapper.cpp
+  rtl_add_top.cpp
+  rtl_add_driver.cpp
+  rtl_add_system.cpp
+)
+
+set(hdrfiles
+  modules/adder_wrapper.hpp
+  modules/client_wrapper.hpp
+  rtl_add_top.hpp
+  rtl_add_driver.hpp
+  rtl_add_system.hpp
+)
+
+add_compile_options(-Wall -Wextra -pedantic)
+
+add_library(design STATIC ${srcfiles} ${hdrfiles})
+target_link_libraries(design PUBLIC SystemC::systemc booksim noc rtl_designs)

rad-sim/example-designs/rtl_add/config.yml

@@ -0,0 +1,37 @@
+noc:
+  type: ['2d']
+  num_nocs: 1
+  clk_period: [1.0]
+  payload_width: [166]
+  topology: ['mesh']
+  dim_x: [4]
+  dim_y: [4] 
+  routing_func: ['dim_order']
+  vcs: [5]
+  vc_buffer_size: [8]
+  output_buffer_size: [8]
+  num_packet_types: [5]
+  router_uarch: ['iq']
+  vc_allocator: ['islip']
+  sw_allocator:  ['islip']
+  credit_delay: [1]
+  routing_delay: [1]
+  vc_alloc_delay: [1]
+  sw_alloc_delay: [1]
+
+noc_adapters:
+  clk_period: [1.25]
+  fifo_size: [16]
+  obuff_size: [2]
+  in_arbiter: ['fixed_rr']
+  out_arbiter: ['priority_rr']
+  vc_mapping: ['direct']
+
+design:
+  name: 'rtl_add'
+  noc_placement: ['rtl_add.place']
+  clk_periods: [5.0]
+
+telemetry:
+  log_verbosity: 2
+  traces: []

rad-sim/example-designs/rtl_add/modules/adder_wrapper.cpp

@@ -0,0 +1,31 @@
+#include <adder_wrapper.hpp>
+#include <Vadder.h>
+
+adder_wrapper::adder_wrapper(const sc_module_name &name) : radsim_module(name) {
+  Vadder* vadder = new Vadder{"vadder"};
+  vadder->clk(clk);
+  vadder->rst(rst);
+  vadder->axis_adder_interface_tvalid(axis_adder_interface.tvalid);
+  vadder->axis_adder_interface_tready(axis_adder_interface.tready);
+  vadder->axis_adder_interface_tlast(axis_adder_interface.tlast);
+  vadder->axis_adder_interface_tdata(axis_adder_interface.tdata);
+  vadder->response(response);
+  vadder->response_valid(response_valid);
+
+  // This function must be defined & called for any RAD-Sim module to register
+  // its info for automatically connecting to the NoC
+  this->RegisterModuleInfo();
+}
+
+adder_wrapper::~adder_wrapper() {}
+
+void adder_wrapper::RegisterModuleInfo() {
+  std::string port_name;
+  _num_noc_axis_slave_ports = 0;
+  _num_noc_axis_master_ports = 0;
+  _num_noc_aximm_slave_ports = 0;
+  _num_noc_aximm_master_ports = 0;
+
+  port_name = module_name + ".axis_adder_interface";
+  RegisterAxisSlavePort(port_name, &axis_adder_interface, DATAW, 0);
+}

rad-sim/example-designs/rtl_add/modules/adder_wrapper.hpp

@@ -0,0 +1,29 @@
+#pragma once
+
+#include <axis_interface.hpp>
+#include <design_context.hpp>
+#include <radsim_defines.hpp>
+#include <radsim_module.hpp>
+#include <string>
+#include <systemc.h>
+#include <vector>
+#include <client_wrapper.hpp>
+
+class adder_wrapper : public radsim_module {
+private:
+  sc_bv<DATAW> adder_rolling_sum; // Sum to store result
+  sc_signal<bool> t_finished; // Signal flagging that the transaction has terminated
+
+public:
+  sc_in<bool> rst;
+  sc_out<bool> response_valid;
+  sc_out<sc_bv<DATAW>> response;
+  // Interface to the NoC
+  axis_slave_port axis_adder_interface;
+
+  adder_wrapper(const sc_module_name &name);
+  ~adder_wrapper();
+
+  SC_HAS_PROCESS(adder_wrapper);
+  void RegisterModuleInfo();
+};

rad-sim/example-designs/rtl_add/modules/client_wrapper.cpp

@@ -0,0 +1,40 @@
+#include <client_wrapper.hpp>
+#include <Vclient.h>
+
+client_wrapper::client_wrapper(const sc_module_name &name) : radsim_module(name) {
+  Vclient* vclient = new Vclient{"vclient"};
+
+  vclient->clk(clk);
+  vclient->rst(rst);
+  vclient->client_tdata(client_tdata);
+  vclient->client_tlast(client_tlast);
+  vclient->client_valid(client_valid);
+  vclient->axis_client_interface_tready(axis_client_interface.tready);
+
+  vclient->client_ready(client_ready);
+  vclient->axis_client_interface_tvalid(axis_client_interface.tvalid);
+  vclient->axis_client_interface_tlast(axis_client_interface.tlast);
+  vclient->axis_client_interface_tdest(axis_client_interface.tdest);
+  vclient->axis_client_interface_tid(axis_client_interface.tid);
+  vclient->axis_client_interface_tstrb(axis_client_interface.tstrb);
+  vclient->axis_client_interface_tkeep(axis_client_interface.tkeep);
+  vclient->axis_client_interface_tuser(axis_client_interface.tuser);
+  vclient->axis_client_interface_tdata(axis_client_interface.tdata);
+
+  // This function must be defined & called for any RAD-Sim module to register
+  // its info for automatically connecting to the NoC
+  this->RegisterModuleInfo();
+}
+
+client_wrapper::~client_wrapper() {}
+
+void client_wrapper::RegisterModuleInfo() {
+  std::string port_name;
+  _num_noc_axis_slave_ports = 0;
+  _num_noc_axis_master_ports = 0;
+  _num_noc_aximm_slave_ports = 0;
+  _num_noc_aximm_master_ports = 0;
+
+  port_name = module_name + ".axis_client_interface";
+  RegisterAxisMasterPort(port_name, &axis_client_interface, DATAW, 0);
+}

rad-sim/example-designs/rtl_add/modules/client_wrapper.hpp

@@ -0,0 +1,31 @@
+#pragma once
+
+#include <axis_interface.hpp>
+#include <design_context.hpp>
+#include <queue>
+#include <radsim_defines.hpp>
+#include <radsim_module.hpp>
+#include <string>
+#include <systemc.h>
+#include <vector>
+
+#define DATAW 128
+
+class client_wrapper : public radsim_module {
+private:
+
+public:
+  sc_in<bool> rst;
+  sc_in<sc_bv<DATAW>> client_tdata;
+  sc_in<bool> client_tlast;
+  sc_in<bool> client_valid;
+  sc_out<bool> client_ready;
+  // Interface to the NoC
+  axis_master_port axis_client_interface;
+
+  client_wrapper(const sc_module_name &name);
+  ~client_wrapper();
+
+  SC_HAS_PROCESS(client_wrapper);
+  void RegisterModuleInfo();
+};

rad-sim/example-designs/rtl_add/modules/rtl/CMakeLists.txt

@@ -0,0 +1,23 @@
+cmake_minimum_required(VERSION 3.19)
+
+find_package(verilator HINTS $ENV{VERILATOR_ROOT})
+if (NOT verilator_FOUND)
+  message(FATAL_ERROR "Verilator was not found. Either install it, or set the VERILATOR_ROOT environment variable")
+endif()
+find_package(SystemCLanguage CONFIG REQUIRED)
+
+set(rtlmodules
+  adder.v
+  client.v
+)
+
+add_library(rtl_designs STATIC)
+target_link_libraries(rtl_designs PUBLIC SystemC::systemc)
+
+foreach(module IN LISTS rtlmodules)
+  verilate(rtl_designs
+    SOURCES ${module}
+    SYSTEMC
+    VERILATOR_ARGS --pins-bv 2 -CFLAGS -std=c++11 -Wno-fatal -Wall
+  )
+endforeach()

rad-sim/example-designs/rtl_add/modules/rtl/adder.v

@@ -0,0 +1,47 @@
+// Adder Module
+// George Trieu
+
+`include "static_params.vh"
+
+module adder (clk, rst, axis_adder_interface_tvalid, axis_adder_interface_tlast, axis_adder_interface_tdata, axis_adder_interface_tready, response, response_valid);
+    input clk;
+    input rst;
+    input axis_adder_interface_tvalid;
+    input axis_adder_interface_tlast;
+    input [`AXIS_MAX_DATAW-1:0] axis_adder_interface_tdata;
+
+	 output reg axis_adder_interface_tready;
+     output reg [`DATAW-1:0] response;
+     output reg response_valid;
+
+    reg [`DATAW-1:0] adder_rolling_sum;
+    reg t_finished;
+
+    always @(rst) begin
+        if (rst) begin
+            adder_rolling_sum = {`DATAW{1'b0}};
+            t_finished = 1'b0;
+            axis_adder_interface_tready = 1'b0;
+        end else begin
+            axis_adder_interface_tready = 1'b1;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            response = {`DATAW{1'b0}};
+            response_valid = 1'b0;
+        end else begin
+            if (axis_adder_interface_tready && axis_adder_interface_tvalid) begin
+                $display("Adder: Received %d!", axis_adder_interface_tdata[63:0]);
+                adder_rolling_sum = adder_rolling_sum + axis_adder_interface_tdata[`DATAW-1:0];
+                t_finished = axis_adder_interface_tlast;
+            end
+
+            if (t_finished) begin
+                response = adder_rolling_sum;
+                response_valid = 1'b1;
+            end
+        end
+    end
+endmodule

rad-sim/example-designs/rtl_add/modules/rtl/client.v

@@ -0,0 +1,84 @@
+// Client Module
+// George Trieu
+
+`include "static_params.vh"
+
+module client (
+	input clk,
+	input rst,
+	input [`DATAW-1:0] client_tdata,
+	input client_tlast,
+	input client_valid,
+	input axis_client_interface_tready,
+	output client_ready,
+	output axis_client_interface_tvalid,
+	output axis_client_interface_tlast,
+	output [`AXIS_DESTW-1:0] axis_client_interface_tdest,
+	output [`AXIS_IDW-1:0] axis_client_interface_tid,
+	output [`AXIS_STRBW-1:0] axis_client_interface_tstrb,
+	output [`AXIS_KEEPW-1:0] axis_client_interface_tkeep,
+	output [`AXIS_USERW-1:0] axis_client_interface_tuser,
+	output [`AXIS_MAX_DATAW-1:0] axis_client_interface_tdata
+);
+
+	 wire fifo_w_en, fifo_r_en;
+	 wire [`DATAW-1:0] fifo_data_in;
+
+	 wire [`DATAW-1:0] fifo_data_out;
+	 wire fifo_full;
+	 wire fifo_empty;
+
+	 reg last_item_latch;
+	 integer item_count;
+
+	 // there is 2 clock cycle delays from the client receiving a LAST flag to when it is 
+
+	 fifo #(.DATA_WIDTH(`DATAW), .DEPTH(`FIFO_DEPTH)) client_tdata_fifo(
+		.clk(clk),
+		.rst(rst),
+		.w_enable(fifo_w_en),
+		.r_enable(fifo_r_en),
+		.data_in(fifo_data_in),
+		.data_out(fifo_data_out),
+		.full(fifo_full),
+		.empty(fifo_empty)
+	 );
+
+	 assign client_ready = ~fifo_full;
+	 assign fifo_r_en = axis_client_interface_tvalid && axis_client_interface_tready;
+	 assign fifo_w_en = client_ready && client_valid;
+	 assign fifo_data_in = client_tdata;
+
+	 assign axis_client_interface_tdest = `DEST_ADDR;
+	 assign axis_client_interface_tuser = `SRC_ADDR;
+	 assign axis_client_interface_tid = {`AXIS_IDW{1'b0}};
+	 assign axis_client_interface_tstrb = {`AXIS_STRBW{1'b0}};
+	 assign axis_client_interface_tkeep = {`AXIS_KEEPW{1'b0}};
+	 assign axis_client_interface_tvalid = ~fifo_empty;
+	 assign axis_client_interface_tdata = fifo_data_out;
+	 assign axis_client_interface_tlast = last_item_latch && item_count == 1;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            item_count <= 0;
+				last_item_latch <= 1'b0;
+        end else begin
+				if (client_ready && client_valid && axis_client_interface_tvalid && axis_client_interface_tready) begin
+					// push data onto the FIFO
+					$display("Client: Added %d onto the FIFO!", client_tdata[63:0]);
+					$display("Client: Sent %d to Adder!", axis_client_interface_tdata[63:0]);
+				end else if (client_ready && client_valid) begin
+					// push data onto the FIFO
+					item_count <= item_count + 1;
+					$display("Client: Added %d onto the FIFO!", client_tdata[63:0]);
+				end else if (axis_client_interface_tvalid && axis_client_interface_tready) begin
+					item_count <= item_count - 1;
+					$display("Client: Sent %d to Adder!", axis_client_interface_tdata[63:0]);
+				end
+
+				if (client_tlast) begin
+					last_item_latch <= 1'b1;
+				end
+        end
+    end
+endmodule