Merge pull request #8 from andrewboutros/dev-gtrieu

Adder Example Design

rad-sim/example-designs/add/CMakeLists.txt

@@ -0,0 +1,33 @@
+cmake_minimum_required(VERSION 3.19)
+find_package(SystemCLanguage CONFIG REQUIRED)
+
+include_directories(
+  ./
+  modules
+  ../../sim
+  ../../sim/noc
+  ../../sim/noc/booksim
+  ../../sim/noc/booksim/networks
+  ../../sim/noc/booksim/routers
+)
+
+set(srcfiles
+  modules/adder.cpp
+  modules/client.cpp
+  add_top.cpp
+  add_driver.cpp
+  add_system.cpp
+)
+
+set(hdrfiles
+  modules/adder.hpp
+  modules/client.hpp
+  add_top.hpp
+  add_driver.hpp
+  add_system.hpp
+)
+
+add_compile_options(-Wall -Wextra -pedantic)
+
+add_library(design STATIC ${srcfiles} ${hdrfiles})
+target_link_libraries(design PUBLIC SystemC::systemc booksim noc)

rad-sim/example-designs/add/add.clks

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+adder_inst 0 0
+client_inst 0 0

rad-sim/example-designs/add/add.place

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+adder_inst 0 0 axis
+client_inst 0 3 axis

rad-sim/example-designs/add/add_driver.cpp

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+#include <add_driver.hpp>
+
+#define NUM_ADDENDS 3
+
+add_driver::add_driver(const sc_module_name &name)
+    : sc_module(name) {
+
+  // Random Seed
+  srand (time(NULL));
+  actual_sum = 0;
+
+  // Generate random numbers to be added together by the adder
+  std::cout << "Generating Random Numbers to be added ..." << std::endl;
+  for (unsigned int i = 0; i < NUM_ADDENDS; i++) {
+    unsigned int r_num = std::rand() % 10 + 1;
+    std::cout << r_num << " ";
+    numbers_to_send.push(r_num);
+    actual_sum += r_num;
+  }
+  std::cout << std::endl << "----------------------------------------" << std::endl;
+
+  SC_CTHREAD(source, clk.pos());
+  SC_CTHREAD(sink, clk.pos());
+}
+
+add_driver::~add_driver() {}
+
+void add_driver::source() {
+  // Reset
+  rst.write(true);
+  client_valid.write(false);
+  wait();
+  rst.write(false);
+  wait();
+
+  while (!numbers_to_send.empty()) {
+    client_tdata.write(numbers_to_send.front());
+    client_tlast.write(numbers_to_send.size() <= 1);
+    client_valid.write(true);
+
+    wait();
+
+    if (client_valid.read() && client_ready.read()) {
+      numbers_to_send.pop();
+    }
+  }
+  client_valid.write(false);
+  std::cout << "Finished sending all numbers to client module!" << std::endl;
+  wait();
+}
+
+void add_driver::sink() {
+  while (!response_valid.read()) {
+    wait();
+  }
+  std::cout << "Received " << response.read().to_uint64() << " sum from the adder!" << std::endl;
+  std::cout << "The actual sum is " << actual_sum << std::endl;
+
+  if (response.read() != actual_sum) std::cout << "FAILURE - Output is not matching!" << std::endl;
+  else std::cout << "SUCCESS - Output is matching!" << std::endl;
+
+  sc_stop();
+}

rad-sim/example-designs/add/add_driver.hpp

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+#pragma once
+
+#include <chrono>
+#include <radsim_config.hpp>
+#include <client.hpp>
+#include <stdlib.h>
+#include <systemc.h>
+#include <time.h>
+#include <queue>
+
+class add_driver : public sc_module {
+private:
+  std::queue<int> numbers_to_send;
+  int actual_sum;
+
+public:
+  sc_in<bool> clk;
+  sc_out<bool> rst;
+  sc_out<sc_bv<DATAW>> client_tdata;
+  sc_out<bool> client_tlast;
+  sc_out<bool> client_valid;
+  sc_in<bool> client_ready;
+  sc_in<sc_bv<DATAW>> response;
+  sc_in<bool> response_valid;
+
+  add_driver(const sc_module_name &name);
+  ~add_driver();
+
+  void source();
+  void sink();
+
+  SC_HAS_PROCESS(add_driver);
+};

rad-sim/example-designs/add/add_system.cpp

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+#include <add_system.hpp>
+
+add_system::add_system(const sc_module_name &name, sc_clock *driver_clk_sig)
+    : sc_module(name) {
+
+  // Instantiate driver
+  driver_inst = new add_driver("driver");
+  driver_inst->clk(*driver_clk_sig);
+  driver_inst->rst(rst_sig);
+  driver_inst->client_tdata(client_tdata_sig);
+  driver_inst->client_tlast(client_tlast_sig);
+  driver_inst->client_valid(client_valid_sig);
+  driver_inst->client_ready(client_ready_sig);
+  driver_inst->response(response_sig);
+  driver_inst->response_valid(response_valid_sig);
+
+  // Instantiate design top-level
+  dut_inst = new add_top("dut");
+  dut_inst->rst(rst_sig);
+  dut_inst->client_tdata(client_tdata_sig);
+  dut_inst->client_tlast(client_tlast_sig);
+  dut_inst->client_valid(client_valid_sig);
+  dut_inst->client_ready(client_ready_sig);
+  dut_inst->response(response_sig);
+  dut_inst->response_valid(response_valid_sig);
+}
+
+add_system::~add_system() {
+  delete driver_inst;
+  delete dut_inst;
+  delete sysclk;
+}

rad-sim/example-designs/add/add_system.hpp

@@ -0,0 +1,26 @@
+#pragma once
+
+#include <add_driver.hpp>
+#include <add_top.hpp>
+#include <chrono>
+#include <vector>
+
+class add_system : public sc_module {
+private:
+  sc_signal<sc_bv<DATAW>> client_tdata_sig;
+  sc_signal<bool> client_tlast_sig;
+  sc_signal<bool> client_valid_sig;
+  sc_signal<bool> client_ready_sig;
+  sc_signal<sc_bv<DATAW>> response_sig;
+  sc_signal<bool> response_valid_sig;
+
+public:
+  sc_signal<bool> rst_sig;
+  sc_clock *sysclk;
+  add_driver *driver_inst;
+  add_top *dut_inst;
+
+  add_system(const sc_module_name &name,
+                           sc_clock *driver_clk_sig);
+  ~add_system();
+};

rad-sim/example-designs/add/add_top.cpp

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+#include <add_top.hpp>
+
+add_top::add_top(const sc_module_name &name)
+    : sc_module(name) {
+
+  std::string module_name_str;
+  char module_name[25];
+
+  module_name_str = "client_inst";
+  std::strcpy(module_name, module_name_str.c_str());
+
+  client_inst = new client(module_name, 16);
+  client_inst->rst(rst);
+  client_inst->client_tdata(client_tdata);
+  client_inst->client_tlast(client_tlast);
+  client_inst->client_valid(client_valid);
+  client_inst->client_ready(client_ready);
+
+  module_name_str = "adder_inst";
+  std::strcpy(module_name, module_name_str.c_str());
+  adder_inst = new adder(module_name);
+  adder_inst->rst(rst);
+  adder_inst->response(response);
+  adder_inst->response_valid(response_valid);
+
+  radsim_design.BuildDesignContext("add.place",
+                                   "add.clks");
+  radsim_design.CreateSystemNoCs(rst);
+  radsim_design.ConnectModulesToNoC();
+}
+
+add_top::~add_top() {
+  delete adder_inst;
+  delete client_inst;
+}

rad-sim/example-designs/add/add_top.hpp

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+#pragma once
+
+#include <radsim_config.hpp>
+#include <adder.hpp>
+#include <client.hpp>
+#include <systemc.h>
+#include <vector>
+
+class add_top : public sc_module {
+private:
+  adder *adder_inst;
+  client *client_inst;
+
+public:
+  sc_in<bool> rst;
+  // Client's interface
+  sc_in<sc_bv<DATAW>> client_tdata;
+  sc_in<bool> client_tlast;
+  sc_in<bool> client_valid;
+  sc_out<bool> client_ready;
+  sc_out<sc_bv<DATAW>> response;
+  sc_out<bool> response_valid;
+
+  add_top(const sc_module_name &name);
+  ~add_top();
+};

rad-sim/example-designs/add/config.yml

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+noc:
+  type: ['2d']
+  num_nocs: 1
+  clk_period: [1.0]
+  payload_width: [166]
+  topology: ['mesh']
+  dim_x: [4]
+  dim_y: [4] 
+  routing_func: ['dim_order']
+  vcs: [5]
+  vc_buffer_size: [8]
+  output_buffer_size: [8]
+  num_packet_types: [5]
+  router_uarch: ['iq']
+  vc_allocator: ['islip']
+  sw_allocator:  ['islip']
+  credit_delay: [1]
+  routing_delay: [1]
+  vc_alloc_delay: [1]
+  sw_alloc_delay: [1]
+
+noc_adapters:
+  clk_period: [1.25]
+  fifo_size: [16]
+  obuff_size: [2]
+  in_arbiter: ['fixed_rr']
+  out_arbiter: ['priority_rr']
+  vc_mapping: ['direct']
+
+design:
+  name: 'add'
+  noc_placement: ['add.place']
+  clk_periods: [5.0]
+
+telemetry:
+  log_verbosity: 2
+  traces: []

rad-sim/example-designs/add/modules/adder.cpp

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+#include <adder.hpp>
+
+adder::adder(const sc_module_name &name)
+    : radsim_module(name) {
+
+  // Combinational logic and its sensitivity list
+  SC_METHOD(Assign);
+  sensitive << rst;
+  // Sequential logic and its clock/reset setup
+  SC_CTHREAD(Tick, clk.pos());
+  reset_signal_is(rst, true); // Reset is active high
+
+  // This function must be defined & called for any RAD-Sim module to register
+  // its info for automatically connecting to the NoC
+  this->RegisterModuleInfo();
+}
+
+adder::~adder() {}
+
+void adder::Assign() {
+  if (rst) {
+    adder_rolling_sum = 0;
+    axis_adder_interface.tready.write(false);
+  } else {
+    // Always ready to accept the transaction
+    axis_adder_interface.tready.write(true);
+  }
+}
+
+void adder::Tick() {
+  response_valid.write(0);
+  response.write(0);
+  wait();
+
+  // Always @ positive edge of the clock
+  while (true) {
+    // Receiving transaction from AXI-S interface
+    if (axis_adder_interface.tvalid.read() &&
+        axis_adder_interface.tready.read()) {
+      uint64_t current_sum = adder_rolling_sum.to_uint64();
+      adder_rolling_sum = current_sum + axis_adder_interface.tdata.read().to_uint64();
+      t_finished.write(axis_adder_interface.tlast.read());
+      std::cout << module_name << ": Got Transaction (user = "
+                << axis_adder_interface.tuser.read().to_uint64() << ") (addend = "
+                << axis_adder_interface.tdata.read().to_uint64() << ")!"
+                << std::endl;
+    }
+
+    // Print Sum and Exit
+    if (t_finished.read()) {
+        response_valid.write(1);
+        response.write(adder_rolling_sum);
+    }
+    wait();
+  }
+}
+
+void adder::RegisterModuleInfo() {
+  std::string port_name;
+  _num_noc_axis_slave_ports = 0;
+  _num_noc_axis_master_ports = 0;
+  _num_noc_aximm_slave_ports = 0;
+  _num_noc_aximm_master_ports = 0;
+
+  port_name = module_name + ".axis_adder_interface";
+  RegisterAxisSlavePort(port_name, &axis_adder_interface, DATAW, 0);
+}