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Issues: alexforencich/verilog-pcie
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Can you give the structure diagram of Verilog-pcie? Like Corundum
#57
opened Sep 28, 2024 by
libero-x
Implementation of the TL and DL functions of the PCIE protocol
#51
opened May 12, 2024 by
KavinGarnet
why I run the test instance of tb , it report cannot import module dma_ram?
#50
opened May 2, 2024 by
zhfff4869
python report the error about the path in dma_psdp_ram.py , why?
#49
opened May 2, 2024 by
zhfff4869
Segmented memory address bug caused by ram_mask_1_reg assertion in dma_if_pcie_rd.v
#46
opened Feb 3, 2024 by
C0L
What name of the Top module name of all the verilogs in rtl folder?
#38
opened Aug 28, 2023 by
asifikbal827
bug in dma_if_pcie_rd when max read request size is set to 4096 bytes
#35
opened Jul 7, 2023 by
EricCSun
dma_read_desc_status_valid not asserted when requesting memory read length > 8
#24
opened Jan 5, 2022 by
filamoon
Add Arria 10 device support
enhancement
New feature or request
#11
opened Feb 3, 2021 by
alexforencich
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