When I am trying this project in AX7203 board, it has KSZ9031RNX PHY, which requires typical 2.5MHz mdc clock and it has mdio interface to communicate with PHY. I am following the NexysVideo project for reference. It does not have mdio interface. I get some negative slack. How can I add MDIO to be able to talk to PHY and what commands should i send to configure PHY ?

[kavyash15]

For mdio interface and mdc I have written a module, which sends data through the interface and for setting the mdc clock I have used mmcm to divide the clock to 25MHz and further a clock divider to divide the signal to 2.5MHz. Below is the fpga.v code for reference.

/*

Copyright (c) 2014-2018 Alex Forencich

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

*/

// Language: Verilog 2001

`resetall
`timescale 1ns / 1ps
`default_nettype none

/*
 * FPGA top-level module
 */
module fpga (
    /*
     * Clock: 100MHz
     * Reset: Push button, active low
     */
    input  wire       clk_in1_p,
    input  wire       clk_in1_n,
    input  wire       resetn,


    /*
     * Ethernet: 1000BASE-T RGMII
     */
    input  wire       phy_rx_clk,
    input  wire [3:0] phy_rxd,
    input  wire       phy_rx_ctl,
    output wire       phy_tx_clk,
    output wire [3:0] phy_txd,
    output wire       phy_tx_ctl,
    output wire       phy_reset_n,
    inout  wire       phy_mdio,
    output  wire      phy_mdc
);

// Clock and reset
wire clk_125mhz_ibufg;
wire clk_125mhz_bufg;
wire mmcm_rst = ~resetn;

// clock parts
wire rst_int;   
wire mmcm_locked;
wire mmcm_clkfb;

//pass in clock through this buf 
IBUFGDS #(
   .DIFF_TERM("FALSE"),
   .IBUF_LOW_PWR("FALSE")   
)
clk_125mhz_ibufg_inst (
   .O   (clk_125mhz_ibufg),
   .I   (clk_in1_p),
   .IB  (clk_in1_n) 
);

//then pass the diff through this buf 
BUFG
clk_125mhz_bufg_in_inst (
    .I(clk_125mhz_ibufg),
    .O(clk_125mhz_bufg)
);

//out of mmcm 
wire clk_mmcm_out;
wire clk_int;

wire clk90_mmcm_out;
wire clk90_int;

wire clk_200_mmcm_out;
wire clk_200_int;

wire mdc_clk, phy_mdc1, phy_mdc2,phy_mdc_clk, phy_mdc_in;

//mmcm for diff
// 125MHz out0, 125 MHz with 90 phase shift out1, 200MHz out2
MMCME2_BASE #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKOUT0_DIVIDE_F(8),
    .CLKOUT0_DUTY_CYCLE(0.5),
    .CLKOUT0_PHASE(0),
    .CLKOUT1_DIVIDE(8),
    .CLKOUT1_DUTY_CYCLE(0.5),
    .CLKOUT1_PHASE(90),
    .CLKOUT2_DIVIDE(5),
    .CLKOUT2_DUTY_CYCLE(0.5),
    .CLKOUT2_PHASE(0),
    .CLKOUT3_DIVIDE(40),
    .CLKOUT3_DUTY_CYCLE(0.5),
    .CLKOUT3_PHASE(0),
    .CLKOUT4_DIVIDE(40),
    .CLKOUT4_DUTY_CYCLE(0.5),
    .CLKOUT4_PHASE(0),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.5),
    .CLKOUT5_PHASE(0),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.5),
    .CLKOUT6_PHASE(0),
    .CLKFBOUT_MULT_F(10),
    .CLKFBOUT_PHASE(0),
    .DIVCLK_DIVIDE(1),
    .REF_JITTER1(0.010),
    .CLKIN1_PERIOD(10.0),
    .STARTUP_WAIT("FALSE"),
    .CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
    .CLKIN1(clk_125mhz_bufg),
    .CLKFBIN(mmcm_clkfb),
    .RST(mmcm_rst),
    .PWRDWN(1'b0),
    .CLKOUT0(clk_mmcm_out),
    .CLKOUT0B(),
    .CLKOUT1(clk90_mmcm_out),
    .CLKOUT1B(),
    .CLKOUT2(clk_200_mmcm_out),
    .CLKOUT2B(),
    .CLKOUT3(mdc_clk),
    .CLKOUT3B(),
    .CLKOUT4(phy_mdc_clk),
    .CLKOUT5(),
    .CLKOUT6(),
    .CLKFBOUT(mmcm_clkfb),
    .CLKFBOUTB(),
    .LOCKED(mmcm_locked)
);

BUFG
clk_bufg_inst (
    .I(clk_mmcm_out),
    .O(clk_int)
);

BUFG
clk_bufg_inst_mdc (
    .I(phy_mdc_clk),
    .O(phy_mdc2)
);
BUFG
clkmdc_bufg_inst (
    .I(mdc_clk),
    .O(phy_mdc1)
);

BUFG
clk90_bufg_inst (
    .I(clk90_mmcm_out),
    .O(clk90_int)
);

BUFG
clk_200_bufg_inst (
    .I(clk_200_mmcm_out),
    .O(clk_200_int)
);

sync_reset #(
    .N(4)
)
sync_reset_inst (
    .clk(clk_int),
    .rst(~mmcm_locked),
    .out(rst_int)
);


// 1 div to mdc
reg [3:0] counter = 4'd0;

always @(posedge phy_mdc2) begin //25
  if (counter == 4'd10) begin  // Divide by 10
    counter <= 4'd0;
  end else begin
    counter <= counter + 1'b1 ;
  end
end

assign phy_mdc = (counter == 4'd0);  // Generate 2.5 MHz clock

// 2 div to mdio mod 
reg [3:0] coun = 4'd0;

always @(posedge phy_mdc1) begin //25
  if (coun == 4'd10) begin  // Divide by 10
    coun <= 4'd0;
  end else begin
    coun <= counter + 1'b1 ;
  end
end

assign phy_mdc_in = (coun == 4'd0);  // Generate 2.5 MHz clock
 
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_delay;
wire       phy_rx_ctl_delay;

IDELAYCTRL
idelayctrl_inst
(
    .REFCLK(clk_200_int),
    .RST(rst_int),
    .RDY()
);

IDELAYE2 #(
    .IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_0
(
    .IDATAIN(phy_rxd[0]),
    .DATAOUT(phy_rxd_delay[0]),
    .DATAIN(1'b0),
    .C(1'b0),
    .CE(1'b0),
    .INC(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(5'd0),
    .CNTVALUEOUT(),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(1'b0)
);

IDELAYE2 #(
    .IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_1
(
    .IDATAIN(phy_rxd[1]),
    .DATAOUT(phy_rxd_delay[1]),
    .DATAIN(1'b0),
    .C(1'b0),
    .CE(1'b0),
    .INC(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(5'd0),
    .CNTVALUEOUT(),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(1'b0)
);

IDELAYE2 #(
    .IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_2
(
    .IDATAIN(phy_rxd[2]),
    .DATAOUT(phy_rxd_delay[2]),
    .DATAIN(1'b0),
    .C(1'b0),
    .CE(1'b0),
    .INC(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(5'd0),
    .CNTVALUEOUT(),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(1'b0)
);

IDELAYE2 #(
    .IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_3
(
    .IDATAIN(phy_rxd[3]),
    .DATAOUT(phy_rxd_delay[3]),
    .DATAIN(1'b0),
    .C(1'b0),
    .CE(1'b0),
    .INC(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(5'd0),
    .CNTVALUEOUT(),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(1'b0)
);

IDELAYE2 #(
    .IDELAY_TYPE("FIXED")
)
phy_rx_ctl_idelay
(
    .IDATAIN(phy_rx_ctl),
    .DATAOUT(phy_rx_ctl_delay),
    .DATAIN(1'b0),
    .C(1'b0),
    .CE(1'b0),
    .INC(1'b0),
    .CINVCTRL(1'b0),
    .CNTVALUEIN(5'd0),
    .CNTVALUEOUT(),
    .LD(1'b0),
    .LDPIPEEN(1'b0),
    .REGRST(1'b0)
);

//MDIO INTERFACE //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
wire mdio_o;
wire mdio_t;
wire mdio_i;

ethernet_mdio mdioo(
    .clk(phy_mdc_in),                // clock signal posedge 
    .resetn(rst_int),             // active low reset
    .mdio_i(mdio_i),
    .mdio_o(mdio_o),
    .mdio_t(mdio_t)
);
assign mdio_i = phy_mdio;
assign phy_mdio = mdio_t ? mdio_t : mdio_o; //check
//changed mdio for the  rgmii and the KSZ9031RNX chip  
//mdc clock is 2.5Mhz/25MHz
////////////////////////////////////////////////////////////////////////////////////////////////////////
fpga_core #(
    .TARGET("XILINX")
)
core_inst (
    /*
     * Clock: 125MHz
     * Synchronous reset
     */
    .clk(clk_int),
    .clk90(clk90_int),
    .rst(rst_int),
    /*
     * Ethernet: 1000BASE-T RGMII
     */
    .phy_rx_clk(phy_rx_clk),
    .phy_rxd(phy_rxd_delay),
    .phy_rx_ctl(phy_rx_ctl_delay),
    .phy_tx_clk(phy_tx_clk),
    .phy_txd(phy_txd),
    .phy_tx_ctl(phy_tx_ctl),
    .phy_reset_n(phy_reset_n)
);

endmodule

`resetall

For MDIO,

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
// 
// Create Date: 
// Design Name: 
// Module Name: ethernet_mdio
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`resetall
`timescale 1ns / 1ps
`default_nettype none

module ethernet_mdio(
    input wire clk,                // clock signal posedge 
    input wire resetn,             // active low reset
    input wire mdio_i,
    output reg mdio_o ,
    output reg mdio_t
);
    parameter [2:0] GAP1 = 3'd0 ,
    COMMAND1 = 3'd1,
    GAP2=  3'd2,
    COMMAND2 = 3'd3, 
    GAP3 = 3'd4, 
    COMMAND3 = 3'd5,
    DONE = 3'd6 ;
      
    reg [2:0] state_reg = GAP1;
    reg [6:0] gap_counter = 7'b0;
    reg [6:0] bit_counter = 7'd0;
    reg mdio_i_reg = 1'b0;
    reg [31:0] command1 = 32'b00000000100011000100000100001010;  // Command 1
    reg [31:0] command2 = 32'b00000000000000000110010100001010;  // Command 2
    reg [31:0] command3 = 32'b00000000110011000100000100001010;  // Command 3
    

    
    // Initial conditions or reset conditions
    always @(posedge clk ) begin
        if (!resetn) begin
            state_reg  <= GAP1;
            gap_counter <= 7'd0;
            bit_counter <= 7'd0;
            mdio_o <= 1'b0;  // Initialize mdio_o
            mdio_t <= 1'b1;  // Initialize mdio_t
            mdio_i_reg <= 1'b0;
        end else begin
            mdio_i_reg <= mdio_i;
            case(state_reg) 
                GAP1: begin
                    mdio_o <= 1'b0;
                    mdio_t <= 1'b1;
                    if (gap_counter < 7'd64) begin
                        gap_counter <= gap_counter + 1'b1;
                    end else begin
                        gap_counter <= 7'd0;
                        state_reg <= COMMAND1;
                        bit_counter <= 7'd0;
                    end
                end

                COMMAND1: begin
                    if (bit_counter < 7'd32) begin
                        mdio_t <= 1'b0;
                        mdio_o <= 1'b1;
                        bit_counter <= bit_counter + 1'b1;
                    end else if (bit_counter < 7'd64) begin
                        mdio_t <= 1'b0;
                        mdio_o <= command1[bit_counter - 7'd32];
                        bit_counter <= bit_counter + 1'b1;
                    end else begin
                        mdio_t <= 1'b1;
                        mdio_o <= 1'b0;
                        bit_counter <= 7'b0;
                        state_reg <= GAP2; 
                    end
                end

                GAP2: begin
                    mdio_o <= 1'b0;
                    mdio_t <= 1'b1;
                    if (gap_counter < 7'd64) begin
                        gap_counter <= gap_counter + 1'b1;
                    end else begin
                        gap_counter <= 7'b0;
                        state_reg <= COMMAND2;
                        bit_counter <= 7'b0;
                    end
                end

                COMMAND2: begin
                    if (bit_counter < 7'd32) begin
                        mdio_t <= 1'b0;
                        mdio_o <= 1'b1;
                        bit_counter <= bit_counter + 1'b1;
                    end else if (bit_counter < 7'd64) begin
                        mdio_t <= 1'b0;
                        mdio_o <= command2[bit_counter - 7'd32];
                        bit_counter <= bit_counter + 1'b1;
                    end else begin
                        mdio_t <= 1'b1;
                        mdio_o <= 1'b0;
                        bit_counter <= 7'b0;
                        state_reg <= GAP3; 
                    end
                end

                GAP3: begin
                    mdio_o <= 1'b0;
                    mdio_t <= 1'b1;
                    if (gap_counter < 7'd64) begin
                        gap_counter <= gap_counter + 1'b1;
                    end else begin
                        gap_counter <= 7'b0;
                        state_reg <= COMMAND3;
                        bit_counter <= 7'b0;
                    end
                end

                COMMAND3: begin
                    if (bit_counter < 7'd32) begin
                        mdio_t <= 1'b0;
                        mdio_o <= 1'b1;
                        bit_counter <= bit_counter + 1'b1;
                    end else if (bit_counter < 7'd64) begin
                        mdio_t <= 1'b0;
                        mdio_o <= command3[bit_counter - 7'd32];
                        bit_counter <= bit_counter + 1'b1;
                    end else begin
                        mdio_t <= 1'b1;
                        mdio_o <= 1'b0;
                        bit_counter <= 7'b0;
                        state_reg <= DONE; 
                    end
                end

                DONE: begin
                    mdio_t <= 1'b1;
                    mdio_o <= 1'b0;
                end

            endcase
        end
        end 

endmodule

`resetall

mmcm cannot directly generate 2.5MHz frequency too. so i am stuck.

[kavyash15]

KSZ9031RNX-Datasheet.pdf
This is the datasheet for that PHY.