How do I adapt rgmii_phy_if.v for use with Lattice ECP5 primitives for IODDR and Clock input style?

[t1ch]

I am trying to use verilog-ethernet with a Butterstick FPGA board which has a Lattice ECP5 part. What changes do I need to make to adapt rgmii_phy_if.v to use lattice ECP5 primitives for IODDR style and Clock input style? I have looked up the Lattice FPGA Libraries Reference Guide 3.11 SP3 and identified that for the IODDR there are two primitives that can be used for Input and Output namely IDDRX1F and ODDRX1F.