Discussions

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  How to connect the dut to the bus

  RasmusGOlsen asked Sep 17, 2025 in Q&A · Unanswered

  

  

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  AXIRam component deasserts wready after 2 cycles

  jefflieu asked Mar 4, 2025 in Q&A · Unanswered

  

  

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  initializing AXIL instances defined as unpacked SystemVerilog

  jhuryszblvt asked Jan 14, 2025 in Q&A · Unanswered

  

  

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  Can we vary AxiRam response delays ?

  0BAB1 asked Nov 21, 2024 in Q&A · Unanswered

  

  

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  Welcome to cocotbext-axi Discussions!

  alexforencich started Apr 14, 2021 in General

  

  

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  Tutorial on Using AXI Stream Interfaces for Verification

  mohannithin asked Dec 8, 2023 in Q&A · Unanswered

  

  

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  flow control

  thenameisT started Dec 5, 2023 in General

  

  

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  Timeout on AXI reads and writes

  davekeeshan started Oct 27, 2023 in Ideas

  

  

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  Mid frame AXIS pausing+backpressuring

  OCElephant started Aug 7, 2023 in General · Closed

  

  

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  Disable ID response check

  davekeeshan started Jul 11, 2023 in General

  

  

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  Random backpressure on ready/valid

  davekeeshan asked Feb 14, 2023 in Q&A · Answered

  

  

  

  

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  Setting logging level of Axi classes

  adrianholmesspire started Feb 15, 2023 in General

  

  

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  callbacks from AxiStreamMonitor

  adi8v asked Dec 20, 2022 in Q&A · Unanswered

  

  

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