Timeout on AXI reads and writes

[davekeeshan]

I haven't investigated the code yet (other than to know it is not implemented).

How hard would it to be to add a timeout on the AXI read/write master. When developing, sometimes my slave goes weird and doesn't reply. This causes an simulation hang in cadence tools (incisive/xcelium) that can only be exited by a system kill on the tool. IN most cases, I know that if I am not getting a reply in 1000 clock cycles, then I never will.

A time out with a exception would be a big improvement on what I have right now.

[alexforencich]

Maybe a with_timeout() can be added to read() and write(). That would presumably be the most straightforward implementation.

[davekeeshan]

I didn't understand this answer completely until today.

I was thinking a timeout by default, typically you don't know in advance the read or write that is going to hang, until it hangs, and this is when you want it.

I have been fiddling with some code, I think I have a working solution, I just need to tidy it up.