Add reset_active_level parameters

alexforencich · Mar 7, 2021 · 35ed147 · 35ed147
1 parent a7fe5d9
commit 35ed147
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Showing 7 changed files with 67 additions and 58 deletions.
diff --git a/README.md b/README.md
@@ -78,6 +78,7 @@ Second, blocking operations can be carried out with `read()` and `write()` and t
 * _bus_: `AxiBus` or `AxiLiteBus` object containing AXI interface signals
 * _clock_: clock signal
 * _reset_: reset signal (optional)
+* _reset_active_level_: reset active level (optional, default `True`)
 
 #### Additional parameters for `AxiMaster`
 
@@ -166,6 +167,7 @@ Multi-port memories can be constructed by passing the `mem` object of the first
 * _bus_: `AxiBus` or `AxiLiteBus` object containing AXI interface signals
 * _clock_: clock signal
 * _reset_: reset signal (optional)
+* _reset_active_level_: reset active level (optional, default `True`)
 * _size_: memory size in bytes (optional, default 1024)
 * _mem_: mmap object to use (optional, overrides _size_)
 
@@ -242,6 +244,7 @@ To receive data with an `AxiStreamSink` or `AxiStreamMonitor`, call `recv()`/`re
 * _bus_: `AxiStreamBus` object containing AXI stream interface signals
 * _clock_: clock signal
 * _reset_: reset signal (optional)
+* _reset_active_level_: reset active level (optional, default `True`)
 * _byte_size_: byte size (optional)
 * _byte_lanes_: byte lane count (optional)
 

diff --git a/cocotbext/axi/axi_master.py b/cocotbext/axi/axi_master.py
@@ -49,17 +49,17 @@
 
 
 class AxiMasterWrite(Reset):
-    def __init__(self, bus, clock, reset=None, max_burst_len=256):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI master (write)")
         self.log.info("cocotbext-axi version %s", __version__)
         self.log.info("Copyright (c) 2020 Alex Forencich")
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
-        self.aw_channel = AxiAWSource(bus.aw, clock, reset)
-        self.w_channel = AxiWSource(bus.w, clock, reset)
-        self.b_channel = AxiBSink(bus.b, clock, reset)
+        self.aw_channel = AxiAWSource(bus.aw, clock, reset, reset_active_level)
+        self.w_channel = AxiWSource(bus.w, clock, reset, reset_active_level)
+        self.b_channel = AxiBSink(bus.b, clock, reset, reset_active_level)
 
         self.write_command_queue = deque()
         self.write_command_sync = Event()
@@ -103,7 +103,7 @@ def __init__(self, bus, clock, reset=None, max_burst_len=256):
         self._process_write_cr = None
         self._process_write_resp_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def init_write(self, address, data, awid=None, burst=AxiBurstType.INCR, size=None, lock=AxiLockType.NORMAL,
             cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0, wuser=0, event=None):
@@ -402,16 +402,16 @@ async def _process_write_resp(self):
 
 
 class AxiMasterRead(Reset):
-    def __init__(self, bus, clock, reset=None, max_burst_len=256):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI master (read)")
         self.log.info("cocotbext-axi version %s", __version__)
         self.log.info("Copyright (c) 2020 Alex Forencich")
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
-        self.ar_channel = AxiARSource(bus.ar, clock, reset)
-        self.r_channel = AxiRSink(bus.r, clock, reset)
+        self.ar_channel = AxiARSource(bus.ar, clock, reset, reset_active_level)
+        self.r_channel = AxiRSink(bus.r, clock, reset, reset_active_level)
 
         self.read_command_queue = deque()
         self.read_command_sync = Event()
@@ -453,7 +453,7 @@ def __init__(self, bus, clock, reset=None, max_burst_len=256):
         self._process_read_cr = None
         self._process_read_resp_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def init_read(self, address, length, arid=None, burst=AxiBurstType.INCR, size=None,
             lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0, event=None):
@@ -737,12 +737,12 @@ async def _process_read_resp(self):
 
 
 class AxiMaster:
-    def __init__(self, bus, clock, reset=None, max_burst_len=256):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_len=256):
         self.write_if = None
         self.read_if = None
 
-        self.write_if = AxiMasterWrite(bus.write, clock, reset, max_burst_len)
-        self.read_if = AxiMasterRead(bus.read, clock, reset, max_burst_len)
+        self.write_if = AxiMasterWrite(bus.write, clock, reset, reset_active_level, max_burst_len)
+        self.read_if = AxiMasterRead(bus.read, clock, reset, reset_active_level, max_burst_len)
 
     def init_read(self, address, length, arid=None, burst=AxiBurstType.INCR, size=None,
             lock=AxiLockType.NORMAL, cache=0b0011, prot=AxiProt.NONSECURE, qos=0, region=0, user=0, event=None):

diff --git a/cocotbext/axi/axi_ram.py b/cocotbext/axi/axi_ram.py
@@ -34,7 +34,7 @@
 
 
 class AxiRamWrite(Memory, Reset):
-    def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI RAM model (write)")
@@ -44,9 +44,9 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         super().__init__(size, mem, *args, **kwargs)
 
-        self.aw_channel = AxiAWSink(bus.aw, clock, reset)
-        self.w_channel = AxiWSink(bus.w, clock, reset)
-        self.b_channel = AxiBSource(bus.b, clock, reset)
+        self.aw_channel = AxiAWSink(bus.aw, clock, reset, reset_active_level)
+        self.w_channel = AxiWSink(bus.w, clock, reset, reset_active_level)
+        self.b_channel = AxiBSource(bus.b, clock, reset, reset_active_level)
 
         self.width = len(self.w_channel.bus.wdata)
         self.byte_size = 8
@@ -67,7 +67,7 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         self._process_write_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def _handle_reset(self, state):
         if state:
@@ -157,7 +157,7 @@ async def _process_write(self):
 
 
 class AxiRamRead(Memory, Reset):
-    def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI RAM model (read)")
@@ -167,8 +167,8 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         super().__init__(size, mem, *args, **kwargs)
 
-        self.ar_channel = AxiARSink(bus.ar, clock, reset)
-        self.r_channel = AxiRSource(bus.r, clock, reset)
+        self.ar_channel = AxiARSink(bus.ar, clock, reset, reset_active_level)
+        self.r_channel = AxiRSource(bus.r, clock, reset, reset_active_level)
 
         self.width = len(self.r_channel.bus.rdata)
         self.byte_size = 8
@@ -187,7 +187,7 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         self._process_read_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def _handle_reset(self, state):
         if state:
@@ -262,11 +262,11 @@ async def _process_read(self):
 
 
 class AxiRam(Memory):
-    def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
         self.write_if = None
         self.read_if = None
 
         super().__init__(size, mem, *args, **kwargs)
 
-        self.write_if = AxiRamWrite(bus.write, clock, reset, mem=self.mem)
-        self.read_if = AxiRamRead(bus.read, clock, reset, mem=self.mem)
+        self.write_if = AxiRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
+        self.read_if = AxiRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
diff --git a/cocotbext/axi/axil_master.py b/cocotbext/axi/axil_master.py
@@ -45,17 +45,17 @@
 
 
 class AxiLiteMasterWrite(Reset):
-    def __init__(self, bus, clock, reset=None):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True):
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI lite master (write)")
         self.log.info("cocotbext-axi version %s", __version__)
         self.log.info("Copyright (c) 2020 Alex Forencich")
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
-        self.aw_channel = AxiLiteAWSource(bus.aw, clock, reset)
-        self.w_channel = AxiLiteWSource(bus.w, clock, reset)
-        self.b_channel = AxiLiteBSink(bus.b, clock, reset)
+        self.aw_channel = AxiLiteAWSource(bus.aw, clock, reset, reset_active_level)
+        self.w_channel = AxiLiteWSource(bus.w, clock, reset, reset_active_level)
+        self.b_channel = AxiLiteBSink(bus.b, clock, reset, reset_active_level)
 
         self.write_command_queue = deque()
         self.write_command_sync = Event()
@@ -85,7 +85,7 @@ def __init__(self, bus, clock, reset=None):
         self._process_write_cr = None
         self._process_write_resp_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def init_write(self, address, data, prot=AxiProt.NONSECURE, event=None):
         if event is not None and not isinstance(event, Event):
@@ -269,16 +269,16 @@ async def _process_write_resp(self):
 
 
 class AxiLiteMasterRead(Reset):
-    def __init__(self, bus, clock, reset=None):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True):
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI lite master (read)")
         self.log.info("cocotbext-axi version %s", __version__)
         self.log.info("Copyright (c) 2020 Alex Forencich")
         self.log.info("https://github.com/alexforencich/cocotbext-axi")
 
-        self.ar_channel = AxiLiteARSource(bus.ar, clock, reset)
-        self.r_channel = AxiLiteRSink(bus.r, clock, reset)
+        self.ar_channel = AxiLiteARSource(bus.ar, clock, reset, reset_active_level)
+        self.r_channel = AxiLiteRSink(bus.r, clock, reset, reset_active_level)
 
         self.read_command_queue = deque()
         self.read_command_sync = Event()
@@ -306,7 +306,7 @@ def __init__(self, bus, clock, reset=None):
         self._process_read_cr = None
         self._process_read_resp_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def init_read(self, address, length, prot=AxiProt.NONSECURE, event=None):
         if event is not None and not isinstance(event, Event):
@@ -477,12 +477,12 @@ async def _process_read_resp(self):
 
 
 class AxiLiteMaster:
-    def __init__(self, bus, clock, reset=None):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True):
         self.write_if = None
         self.read_if = None
 
-        self.write_if = AxiLiteMasterWrite(bus.write, clock, reset)
-        self.read_if = AxiLiteMasterRead(bus.read, clock, reset)
+        self.write_if = AxiLiteMasterWrite(bus.write, clock, reset, reset_active_level)
+        self.read_if = AxiLiteMasterRead(bus.read, clock, reset, reset_active_level)
 
     def init_read(self, address, length, prot=AxiProt.NONSECURE, event=None):
         self.read_if.init_read(address, length, prot, event)

diff --git a/cocotbext/axi/axil_ram.py b/cocotbext/axi/axil_ram.py
@@ -34,7 +34,7 @@
 
 
 class AxiLiteRamWrite(Memory, Reset):
-    def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
         self.log = logging.getLogger(f"cocotb.{bus.aw._entity._name}.{bus.aw._name}")
 
         self.log.info("AXI lite RAM model (write)")
@@ -44,9 +44,9 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         super().__init__(size, mem, *args, **kwargs)
 
-        self.aw_channel = AxiLiteAWSink(bus.aw, clock, reset)
-        self.w_channel = AxiLiteWSink(bus.w, clock, reset)
-        self.b_channel = AxiLiteBSource(bus.b, clock, reset)
+        self.aw_channel = AxiLiteAWSink(bus.aw, clock, reset, reset_active_level)
+        self.w_channel = AxiLiteWSink(bus.w, clock, reset, reset_active_level)
+        self.b_channel = AxiLiteBSource(bus.b, clock, reset, reset_active_level)
 
         self.width = len(self.w_channel.bus.wdata)
         self.byte_size = 8
@@ -64,7 +64,7 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         self._process_write_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def _handle_reset(self, state):
         if state:
@@ -115,7 +115,7 @@ async def _process_write(self):
 
 
 class AxiLiteRamRead(Memory, Reset):
-    def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
         self.log = logging.getLogger(f"cocotb.{bus.ar._entity._name}.{bus.ar._name}")
 
         self.log.info("AXI lite RAM model (read)")
@@ -125,8 +125,8 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         super().__init__(size, mem, *args, **kwargs)
 
-        self.ar_channel = AxiLiteARSink(bus.ar, clock, reset)
-        self.r_channel = AxiLiteRSource(bus.r, clock, reset)
+        self.ar_channel = AxiLiteARSink(bus.ar, clock, reset, reset_active_level)
+        self.r_channel = AxiLiteRSource(bus.r, clock, reset, reset_active_level)
 
         self.width = len(self.r_channel.bus.rdata)
         self.byte_size = 8
@@ -142,7 +142,7 @@ def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs)
 
         self._process_read_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def _handle_reset(self, state):
         if state:
@@ -182,11 +182,11 @@ async def _process_read(self):
 
 
 class AxiLiteRam(Memory):
-    def __init__(self, bus, clock, reset=None, size=1024, mem=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True, size=1024, mem=None, *args, **kwargs):
         self.write_if = None
         self.read_if = None
 
         super().__init__(size, mem, *args, **kwargs)
 
-        self.write_if = AxiLiteRamWrite(bus.write, clock, reset, mem=self.mem)
-        self.read_if = AxiLiteRamRead(bus.read, clock, reset, mem=self.mem)
+        self.write_if = AxiLiteRamWrite(bus.write, clock, reset, reset_active_level, mem=self.mem)
+        self.read_if = AxiLiteRamRead(bus.read, clock, reset, reset_active_level, mem=self.mem)
diff --git a/cocotbext/axi/axis.py b/cocotbext/axi/axis.py
@@ -260,7 +260,9 @@ class AxiStreamBase(Reset):
     _valid_init = None
     _ready_init = None
 
-    def __init__(self, bus, clock, reset=None, byte_size=None, byte_lanes=None, *args, **kwargs):
+    def __init__(self, bus, clock, reset=None, reset_active_level=True,
+            byte_size=None, byte_lanes=None, *args, **kwargs):
+
         self.bus = bus
         self.clock = clock
         self.reset = reset
@@ -339,7 +341,7 @@ def __init__(self, bus, clock, reset=None, byte_size=None, byte_lanes=None, *arg
 
         self._run_cr = None
 
-        self._init_reset(reset)
+        self._init_reset(reset, reset_active_level)
 
     def count(self):
         return len(self.queue)
@@ -518,8 +520,10 @@ class AxiStreamMonitor(AxiStreamBase):
     _valid_init = None
     _ready_init = None
 
-    def __init__(self, bus, clock, reset=None, byte_size=None, byte_lanes=None, *args, **kwargs):
-        super().__init__(bus, clock, reset, byte_size, byte_lanes, *args, **kwargs)
+    def __init__(self, bus, clock, reset=None, reset_active_level=True,
+            byte_size=None, byte_lanes=None, *args, **kwargs):
+
+        super().__init__(bus, clock, reset, reset_active_level, byte_size, byte_lanes, *args, **kwargs)
 
         self.read_queue = []
 
@@ -620,8 +624,10 @@ class AxiStreamSink(AxiStreamMonitor, AxiStreamPause):
     _valid_init = None
     _ready_init = 0
 
-    def __init__(self, bus, clock, reset=None, byte_size=None, byte_lanes=None, *args, **kwargs):
-        super().__init__(bus, clock, reset, byte_size, byte_lanes, *args, **kwargs)
+    def __init__(self, bus, clock, reset=None, reset_active_level=True,
+            byte_size=None, byte_lanes=None, *args, **kwargs):
+
+        super().__init__(bus, clock, reset, reset_active_level, byte_size, byte_lanes, *args, **kwargs)
 
         self.queue_occupancy_limit_bytes = -1
         self.queue_occupancy_limit_frames = -1