riscv_opcode_tidying_operands_1

Cleaning: Opcode Tidying - Operands (Batch 1)

• Status: Merged for Binutils 2.40
• Branch: riscv-opcode-tidying-operands-1
• Tracking PR: #34 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-08-07)
  • PATCH v2 (2022-09-22)

Feature Description

PATCH 1: validate_riscv_insn (Assembler : validation part)

Since validate_riscv_insn function lists three macro-only operand types, this patch adds other three operands. That means, validate_riscv_insn lists all macro-only operand types with this patch.

OpType	Status
A	Existing
B	Existing
I	Existing
c	New
VM	New
VT	New

Note that validate_riscv_insn is called only for non-macro instructions. In the future, we could reject (and make an internal error) when we encountered those macro-only operand types on regular (non-macro) instructions.

PATCH 2: print_insn_args (Disassembler)

There are six unused operand types but "b" should be removed.

• It looks like an alias of the "s" operand type.
• It hasn't used since the beginning.
• Its role is not clear.

OpType	Notes
Cx	RS2 (where rd == rs2), similar to Ct (encoding) and Cw (constraints). Future implementation may use this for new compressed instructions.
Vf, Ve	Used for vector AMO instructions. They are not ratified and instructions are not upstreamed yet. However, only operand types are upstreamed.
[, ]	No usecases but not harmless and their role is clear.
b	See above. Keeping this is considered harmful.