riscv_float_combined_1

RISC-V: Zfinx-related fixes (1)

• Status: Merged for Binutils 2.40
• Branch: riscv-float-combined-1
• Tracking PR: #63 (view Pull Request and Diff)
• Mailing List:
  • PATCH v1 (2022-09-28)

Based On

• Combined floating point enhancements
  This patchset is a subset of this (but modified).

Related

• RISC-V: Zfinx-related fixes (2)

Issues Solved

1. Enhance Zfinx/Zdinx/Zqinx Testcases

I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support patch. I also...

• Made indentation / coding style consistent and clean
• Started to use valid register number (on Zqinx)
• Started to use different register per operand

2. Relax Requirements to fmv.[sdq] instructions

On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not. On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair. That means, single...

fmv.d  x10, x12

is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs):

mv  x10, x12
mv  x11, x13

Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx extensions, it's safe to implement this pseudo-instructions.

This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.

Note that fmv.h instruction is already a part of both Zfh and Zhinx extensions.