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Merge pull request #190 from Xilinx/184-enable-multiple-kernel-builds…
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…-with-different-configurations

184 enable multiple kernel builds with different configurations
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@quetric
quetric authored Apr 12, 2024
2 parents fc521c2 + 4d5c492 commit 4548ec0
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Showing 45 changed files with 298 additions and 332 deletions.
73 changes: 50 additions & 23 deletions kernels/cclo/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -18,31 +18,40 @@
PLATFORM ?= xilinx_u280_xdma_201920_3
HW_DEBUG ?= none
STACK_TYPE ?= UDP
MODE ?= xo
EN_DMA ?= 1
EN_ARITH ?= 1
EN_COMPRESS ?= 1
EN_EXT_KRNL ?= 1
MB_DEBUG_LEVEL ?= 0
SIM_MEM_SIZE_LOG ?= 28
SIM_MEM_LATENCY ?= 50
CCLO_ELF=vitis_ws/ccl_offload_control/Debug/ccl_offload_control.elf
CCLO_SIMDLL=ccl_offload_ex/ccl_offload_ex.sim/sim_1/behav/xsim/xsim.dir/ccl_offload_behav/xsimk.so
CCLO_XSA=ccl_offload_ex/ccl_offload.xsa
CCLO_DCP=ccl_offload_ex/ccl_offload_ex.runs/synth_1/packaged.dcp
CCLO_XO=ccl_offload.xo

FW_SOURCES = $(shell find fw -name '*.c') $(shell find fw -name '*.h') $(shell find fw -name '*.tcl')

ifeq ($(MODE), simdll)
EN_DMA=1
EN_ARITH=1
EN_COMPRESS=1
EN_EXT_KRNL=1
MB_DEBUG_LEVEL=0
endif

ifeq (u250,$(findstring u250, $(PLATFORM)))
FPGAPART=xcu250-figd2104-2L-e
BOARD=u250
else ifeq (u280,$(findstring u280, $(PLATFORM)))
FPGAPART=xcu280-fsvh2892-2L-e
BOARD=u280
else ifeq (u55c,$(findstring u55c, $(PLATFORM)))
FPGAPART=xcu55c-fsvh2892-2L-e
BOARD=u55c
else ifeq (u200,$(findstring u200, $(PLATFORM)))
FPGAPART=xcu200-fsgd2104-2-e
BOARD=u200
else ifeq (u50,$(findstring u50, $(PLATFORM)))
FPGAPART=xcu50-fsvh2104-2-e
BOARD=u50
else
$(error Unsupported PLATFORM)
endif
Expand All @@ -51,14 +60,34 @@ COMMIT_HASH := 0x$(shell git rev-parse HEAD | cut -c 1-6)
GEN_KERNEL_TCL := tcl/generate_kernel.tcl
REBUILD_BD_TCL := tcl/rebuild_bd.tcl tcl/control_bd.tcl tcl/rx_bd.tcl tcl/tx_bd.tcl

all: $(CCLO_XO)
ifeq ($(MODE), simdll)
FPGAPART=xcu280-fsvh2892-2L-e
BOARD=u280
BUILD_FOLDER = $(STACK_TYPE)_sim
else
BUILD_FOLDER = $(STACK_TYPE)_$(EN_DMA)$(EN_ARITH)$(EN_COMPRESS)$(EN_EXT_KRNL)$(MB_DEBUG_LEVEL)_$(FPGAPART)
endif

CCLO_ELF=$(BUILD_FOLDER)/vitis_ws/ccl_offload_control/Debug/ccl_offload_control.elf
CCLO_SIMDLL=$(BUILD_FOLDER)/ccl_offload_ex/ccl_offload_ex.sim/sim_1/behav/xsim/xsim.dir/ccl_offload_behav/xsimk.so
CCLO_XSA=$(BUILD_FOLDER)/ccl_offload.xsa
CCLO_DCP=$(BUILD_FOLDER)/ccl_offload_ex/ccl_offload_ex.runs/synth_1/packaged.dcp
CCLO_XO=$(BUILD_FOLDER)/ccl_offload.xo

OUTPUT_PRODUCT=$(CCLO_XO)
ifeq ($(MODE), simdll)
OUTPUT_PRODUCT=$(CCLO_SIMDLL)
endif

all: $(OUTPUT_PRODUCT)

.PHONY: xsa
xsa: $(CCLO_XSA)

$(CCLO_XSA): $(GEN_KERNEL_TCL) $(REBUILD_BD_TCL)
$(MAKE) -C hls/ DEVICE=$(FPGAPART)
vivado -mode batch -source $< -tclargs $(FPGAPART) $(HW_DEBUG) $(CCLO_XSA) $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(MB_DEBUG_LEVEL) $(COMMIT_HASH)
mkdir -p $(BUILD_FOLDER)
cd $(BUILD_FOLDER) && vivado -mode batch -source ../$< -tclargs $(FPGAPART) $(HW_DEBUG) ./ccl_offload.xsa $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(MB_DEBUG_LEVEL) $(COMMIT_HASH)

OPTIMIZATION=3
#valid values 0,1,2,3,s,g
Expand All @@ -74,36 +103,34 @@ else ifeq ($(OPTIMIZATION),s)
OPTIMIZATION_STRING = "Optimize for size (-Os)"
endif

.PHONY: elf simdll xo clean dcp
.PHONY: elf xo clean dcp

elf: $(CCLO_ELF)

$(CCLO_ELF): tcl/generate_sw.tcl tcl/associate_elf.tcl $(FW_SOURCES) $(CCLO_XSA)
rm -rf vitis_ws && mkdir vitis_ws
xsct $< ccl_offload $(CCLO_XSA) ./fw $(OPTIMIZATION_STRING)
vivado -mode batch -source tcl/associate_elf.tcl -tclargs $(CCLO_ELF)

simdll: $(CCLO_SIMDLL)
cd $(BUILD_FOLDER) && xsct ../tcl/generate_sw.tcl ccl_offload ./ccl_offload.xsa ../fw $(OPTIMIZATION_STRING)
cd $(BUILD_FOLDER) && vivado -mode batch -source ../tcl/associate_elf.tcl -tclargs vitis_ws/ccl_offload_control/Debug/ccl_offload_control.elf

$(CCLO_SIMDLL): tcl/generate_sim.tcl elf
$(MAKE) -C ../plugins PLATFORM=$(PLATFORM) NUM_EXTDMA_AXI=2
vivado -mode batch -source $< -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(SIM_MEM_SIZE_LOG) $(SIM_MEM_LATENCY)
cd ccl_offload_ex/ccl_offload_ex.sim/sim_1/behav/xsim/ && ./compile.sh && ./elaborate.sh
$(MAKE) -C ../plugins DEVICE=$(FPGAPART)
cd $(BUILD_FOLDER) && vivado -mode batch -source ../tcl/generate_sim.tcl -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(SIM_MEM_SIZE_LOG) $(SIM_MEM_LATENCY)
cd $(BUILD_FOLDER)/ccl_offload_ex/ccl_offload_ex.sim/sim_1/behav/xsim/ && ./compile.sh && ./elaborate.sh

dcp: $(CCLO_DCP)

$(CCLO_DCP): tcl/generate_dcp.tcl $(CCLO_ELF)
vivado -mode batch -source $< -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(MB_DEBUG_LEVEL)
cd $(BUILD_FOLDER) && vivado -mode batch -source ../tcl/generate_dcp.tcl -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(MB_DEBUG_LEVEL)

xo: $(CCLO_XO)

ccl_offload.xml:
$(BUILD_FOLDER)/ccl_offload.xml:
python3 gen_xml.py $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL)
mkdir -p $(BUILD_FOLDER)
mv ccl_offload.xml $@

$(CCLO_XO): tcl/generate_xo.tcl ccl_offload.xml $(CCLO_DCP)
rm -rf ccl_offload_ex/ccl_offload
vivado -mode batch -source $< -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(MB_DEBUG_LEVEL)
$(CCLO_XO): tcl/generate_xo.tcl $(BUILD_FOLDER)/ccl_offload.xml $(CCLO_DCP)
rm -rf $(BUILD_FOLDER)/ccl_offload_ex/ccl_offload
cd $(BUILD_FOLDER) && vivado -mode batch -source ../tcl/generate_xo.tcl -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(MB_DEBUG_LEVEL)

clean:
$(MAKE) -C hls/ clean
rm -rf ccl_offload_ex ccl_offload.xml ccl_offload.xo vitis_ws .Xil *.jou *.log
git clean -xfd
64 changes: 0 additions & 64 deletions kernels/cclo/hdl/ccl_offload.v
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Original file line number Diff line number Diff line change
Expand Up @@ -340,70 +340,6 @@ module ccl_offload
`endif

`ifdef DMA_ENABLE
.m_axi_0_araddr(m_axi_0_araddr),
.m_axi_0_arburst(m_axi_0_arburst),
.m_axi_0_arcache(m_axi_0_arcache),
.m_axi_0_arlen(m_axi_0_arlen),
.m_axi_0_arprot(m_axi_0_arprot),
.m_axi_0_arready(m_axi_0_arready),
.m_axi_0_arsize(m_axi_0_arsize),
.m_axi_0_aruser(m_axi_0_aruser),
.m_axi_0_arvalid(m_axi_0_arvalid),
.m_axi_0_awaddr(m_axi_0_awaddr),
.m_axi_0_awburst(m_axi_0_awburst),
.m_axi_0_awcache(m_axi_0_awcache),
.m_axi_0_awlen(m_axi_0_awlen),
.m_axi_0_awprot(m_axi_0_awprot),
.m_axi_0_awready(m_axi_0_awready),
.m_axi_0_awsize(m_axi_0_awsize),
.m_axi_0_awuser(m_axi_0_awuser),
.m_axi_0_awvalid(m_axi_0_awvalid),
.m_axi_0_bready(m_axi_0_bready),
.m_axi_0_bresp(m_axi_0_bresp),
.m_axi_0_bvalid(m_axi_0_bvalid),
.m_axi_0_rdata(m_axi_0_rdata),
.m_axi_0_rlast(m_axi_0_rlast),
.m_axi_0_rready(m_axi_0_rready),
.m_axi_0_rresp(m_axi_0_rresp),
.m_axi_0_rvalid(m_axi_0_rvalid),
.m_axi_0_wdata(m_axi_0_wdata),
.m_axi_0_wlast(m_axi_0_wlast),
.m_axi_0_wready(m_axi_0_wready),
.m_axi_0_wstrb(m_axi_0_wstrb),
.m_axi_0_wvalid(m_axi_0_wvalid),

.m_axi_1_araddr(m_axi_1_araddr),
.m_axi_1_arburst(m_axi_1_arburst),
.m_axi_1_arcache(m_axi_1_arcache),
.m_axi_1_arlen(m_axi_1_arlen),
.m_axi_1_arprot(m_axi_1_arprot),
.m_axi_1_arready(m_axi_1_arready),
.m_axi_1_arsize(m_axi_1_arsize),
.m_axi_1_aruser(m_axi_1_aruser),
.m_axi_1_arvalid(m_axi_1_arvalid),
.m_axi_1_awaddr(m_axi_1_awaddr),
.m_axi_1_awburst(m_axi_1_awburst),
.m_axi_1_awcache(m_axi_1_awcache),
.m_axi_1_awlen(m_axi_1_awlen),
.m_axi_1_awprot(m_axi_1_awprot),
.m_axi_1_awready(m_axi_1_awready),
.m_axi_1_awsize(m_axi_1_awsize),
.m_axi_1_awuser(m_axi_1_awuser),
.m_axi_1_awvalid(m_axi_1_awvalid),
.m_axi_1_bready(m_axi_1_bready),
.m_axi_1_bresp(m_axi_1_bresp),
.m_axi_1_bvalid(m_axi_1_bvalid),
.m_axi_1_rdata(m_axi_1_rdata),
.m_axi_1_rlast(m_axi_1_rlast),
.m_axi_1_rready(m_axi_1_rready),
.m_axi_1_rresp(m_axi_1_rresp),
.m_axi_1_rvalid(m_axi_1_rvalid),
.m_axi_1_wdata(m_axi_1_wdata),
.m_axi_1_wlast(m_axi_1_wlast),
.m_axi_1_wready(m_axi_1_wready),
.m_axi_1_wstrb(m_axi_1_wstrb),
.m_axi_1_wvalid(m_axi_1_wvalid),
`elsif DMA_EXTERNAL
.m_axis_dma0_s2mm_tdata(m_axis_dma0_s2mm_tdata),
.m_axis_dma0_s2mm_tkeep(m_axis_dma0_s2mm_tkeep),
.m_axis_dma0_s2mm_tdest(m_axis_dma0_s2mm_tdest),
Expand Down
2 changes: 1 addition & 1 deletion kernels/cclo/hls/build.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ set seg_dir "[pwd]/../segmenter/"
set rx_dir "[pwd]/../rxbuf_offload/"
set drv_dir "[pwd]/../../../../driver/hls/"

open_project build_$ipname
open_project build_${ipname}.${device}

add_files $ipname.cpp -cflags "-std=c++14 -I. -I../ -I$drv_dir -I$hlslib_dir -I$fw_dir -I$eth_dir -I$seg_dir -I$rx_dir -DACCL_SYNTHESIS"
if {$do_sim || $do_cosim} {
Expand Down
2 changes: 1 addition & 1 deletion kernels/cclo/hls/dma_mover/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@

TARGET=ip
DEVICE=xcu280-fsvh2892-2L-e
DMA_MOVER_IP=build_dma_mover/sol1/impl/ip/xilinx_com_hls_dma_mover_1_0.zip
DMA_MOVER_IP=build_dma_mover.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_dma_mover_1_0.zip

all: $(DMA_MOVER_IP)

Expand Down
2 changes: 1 addition & 1 deletion kernels/cclo/hls/dma_mover/build_dma_mover.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ switch $command {
}
}

open_project build_dma_mover
open_project build_dma_mover.${device}

add_files dma_mover.cpp -cflags "-std=c++14 -I[pwd]/../../../../driver/hls -I[pwd]/../eth_intf/ -I[pwd]/../../../../hlslib/include/hlslib/xilinx -I[pwd]/../segmenter -I[pwd]/../../fw/sw_apps/ccl_offload_control/src -DHLSLIB_SYNTHESIS"
add_files -tb tb_dma_mover.cpp -cflags "-std=c++14 -I[pwd]/../../../../driver/hls -I[pwd]/../eth_intf/ -I[pwd]/../../../../hlslib/include/hlslib/xilinx -I[pwd]/../segmenter -I[pwd]/../../fw/sw_apps/ccl_offload_control/src -DHLSLIB_SYNTHESIS"
Expand Down
18 changes: 9 additions & 9 deletions kernels/cclo/hls/eth_intf/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -16,15 +16,15 @@
# *******************************************************************************/

DEVICE=xcu280-fsvh2892-2L-e
TCP_PACKETIZER_IP=build_tcp_packetizer/sol1/impl/ip/xilinx_com_hls_tcp_packetizer_1_0.zip
TCP_DEPACKETIZER_IP=build_tcp_depacketizer/sol1/impl/ip/xilinx_com_hls_tcp_depacketizer_1_0.zip
TCP_TXHANDLER_IP=build_tcp_txHandler//sol1/impl/ip/xilinx_com_hls_tcp_txHandler_1_0.zip
TCP_RXHANDLER_IP=build_tcp_rxHandler//sol1/impl/ip/xilinx_com_hls_tcp_rxHandler_1_0.zip
UDP_PACKETIZER_IP=build_udp_packetizer/sol1/impl/ip/xilinx_com_hls_udp_packetizer_1_0.zip
UDP_DEPACKETIZER_IP=build_udp_depacketizer/sol1/impl/ip/xilinx_com_hls_udp_depacketizer_1_0.zip
RDMA_SQ_HANDLER_IP=build_rdma_sq_handler/sol1/impl/ip/xilinx_com_hls_rdma_sq_handler_1_0.zip
RDMA_PACKETIZER_IP=build_rdma_packetizer/sol1/impl/ip/xilinx_com_hls_rdma_packetizer_1_0.zip
RDMA_DEPACKETIZER_IP=build_rdma_depacketizer/sol1/impl/ip/xilinx_com_hls_rdma_depacketizer_1_0.zip
TCP_PACKETIZER_IP=build_tcp_packetizer.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_tcp_packetizer_1_0.zip
TCP_DEPACKETIZER_IP=build_tcp_depacketizer.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_tcp_depacketizer_1_0.zip
TCP_TXHANDLER_IP=build_tcp_txHandler.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_tcp_txHandler_1_0.zip
TCP_RXHANDLER_IP=build_tcp_rxHandler.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_tcp_rxHandler_1_0.zip
UDP_PACKETIZER_IP=build_udp_packetizer.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_udp_packetizer_1_0.zip
UDP_DEPACKETIZER_IP=build_udp_depacketizer.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_udp_depacketizer_1_0.zip
RDMA_SQ_HANDLER_IP=build_rdma_sq_handler.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rdma_sq_handler_1_0.zip
RDMA_PACKETIZER_IP=build_rdma_packetizer.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rdma_packetizer_1_0.zip
RDMA_DEPACKETIZER_IP=build_rdma_depacketizer.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rdma_depacketizer_1_0.zip

TARGET=ip

Expand Down
8 changes: 4 additions & 4 deletions kernels/cclo/hls/rxbuf_offload/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,10 @@

TARGET=ip
DEVICE=xcu250-figd2104-2L-e
RXBUF_DEQUEUE_IP=build_rxbuf_dequeue/sol1/impl/ip/xilinx_com_hls_rxbuf_dequeue_1_0.zip
RXBUF_ENQUEUE_IP=build_rxbuf_enqueue/sol1/impl/ip/xilinx_com_hls_rxbuf_enqueue_1_0.zip
RXBUF_SEEK_IP=build_rxbuf_seek/sol1/impl/ip/xilinx_com_hls_rxbuf_seek_1_0.zip
RXBUF_SESSION_IP=build_rxbuf_session/sol1/impl/ip/xilinx_com_hls_rxbuf_session_1_0.zip
RXBUF_DEQUEUE_IP=build_rxbuf_dequeue.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rxbuf_dequeue_1_0.zip
RXBUF_ENQUEUE_IP=build_rxbuf_enqueue.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rxbuf_enqueue_1_0.zip
RXBUF_SEEK_IP=build_rxbuf_seek.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rxbuf_seek_1_0.zip
RXBUF_SESSION_IP=build_rxbuf_session.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_rxbuf_session_1_0.zip

all: $(RXBUF_DEQUEUE_IP) $(RXBUF_ENQUEUE_IP) $(RXBUF_SEEK_IP) $(RXBUF_SESSION_IP)

Expand Down
4 changes: 2 additions & 2 deletions kernels/cclo/hls/segmenter/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,8 @@
# *******************************************************************************/

DEVICE=xcu250-figd2104-2L-e
SEGMENTER_IP=build_stream_segmenter/sol1/impl/ip/xilinx_com_hls_stream_segmenter_1_0.zip
DMA2SEGCMD_IP=build_dma2seg_cmd/sol1/impl/ip/xilinx_com_hls_dma2seg_cmd_1_0.zip
SEGMENTER_IP=build_stream_segmenter.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_stream_segmenter_1_0.zip
DMA2SEGCMD_IP=build_dma2seg_cmd.$(DEVICE)/sol1/impl/ip/xilinx_com_hls_dma2seg_cmd_1_0.zip
TARGET=ip

all: $(SEGMENTER_IP) $(DMA2SEGCMD_IP)
Expand Down
22 changes: 11 additions & 11 deletions kernels/cclo/tcl/generate_kernel.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -34,36 +34,36 @@ update_compile_order -fileset sources_1
create_bd_design ccl_offload_bd

# add our own ip to the repo
set_property ip_repo_paths {./hls/} [current_project]
set_property ip_repo_paths {../hls/} [current_project]
update_ip_catalog

#rebuild bd
source -notrace tcl/rebuild_bd.tcl
source -notrace ../tcl/rebuild_bd.tcl
create_root_design $stacktype $en_dma $en_arith $en_compress $en_extkrnl $mb_debug_level $commit_hash

#add debug if requested
if [string equal $hw_debug_level "dma"] {
puts "Adding DMA debug to block design"
source -notrace tcl/debug_dma.tcl
source -notrace ../tcl/debug_dma.tcl
} elseif [string equal $hw_debug_level "pkt"] {
puts "Adding (de)packetizer debug to block design"
source -notrace tcl/debug_pkt.tcl
source -notrace ../tcl/debug_pkt.tcl
} elseif [string equal $hw_debug_level "arith"] {
puts "Adding arithmetic debug to block design"
source -notrace tcl/debug_arith.tcl
source -notrace ../tcl/debug_arith.tcl
} elseif [string equal $hw_debug_level "control"] {
puts "Adding control debug to block design"
source -notrace tcl/debug_control.tcl
source -notrace ../tcl/debug_control.tcl
} elseif [string equal $hw_debug_level "all"] {
puts "Adding all debug cores to block design"
source -notrace tcl/debug_dma.tcl
source -notrace tcl/debug_pkt.tcl
source -notrace tcl/debug_arith.tcl
source -notrace tcl/debug_control.tcl
source -notrace ../tcl/debug_dma.tcl
source -notrace ../tcl/debug_pkt.tcl
source -notrace ../tcl/debug_arith.tcl
source -notrace ../tcl/debug_control.tcl
}

# add wrapper
add_files -norecurse ./hdl/ccl_offload.v
add_files -norecurse ../hdl/ccl_offload.v
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
generate_target all [get_files ./ccl_offload_ex/ccl_offload_ex.srcs/sources_1/bd/ccl_offload_bd/ccl_offload_bd.bd]
Expand Down
10 changes: 6 additions & 4 deletions kernels/cclo/tcl/generate_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -38,11 +38,11 @@ open_project ./ccl_offload_ex/ccl_offload_ex.xpr
update_compile_order -fileset sim_1

# add plugins to the catalog
set_property ip_repo_paths { ./hls ./../plugins } [current_project]
set_property ip_repo_paths { ../hls ../../plugins } [current_project]
update_ip_catalog

# add the simulation memory to the project
add_files -norecurse ./hdl/sim_mem.v
add_files -norecurse ../hdl/sim_mem.v
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

Expand Down Expand Up @@ -141,15 +141,15 @@ if { $en_dma != 0 } {
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_2/M00_AXI] [get_bd_intf_pins axi_crossbar_0/S02_AXI]
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_2/M01_AXI] [get_bd_intf_pins axi_crossbar_1/S02_AXI]

create_bd_cell -type ip -vlnv Xilinx:ACCL:external_dma:1.0 external_dma_0
create_bd_cell -type ip -vlnv Xilinx:ACCL:external_dma_2port:1.0 external_dma_0
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins external_dma_0/ap_clk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins external_dma_0/ap_rst_n]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/m_axi_0] [get_bd_intf_pins axi_crossbar_0/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/m_axi_1] [get_bd_intf_pins axi_crossbar_1/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/s_axis_s2mm] [get_bd_intf_pins cclo/m_axis_dma0_s2mm]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/m_axis_mm2s] [get_bd_intf_pins cclo/s_axis_dma0_mm2s]

create_bd_cell -type ip -vlnv Xilinx:ACCL:external_dma:1.0 external_dma_1
create_bd_cell -type ip -vlnv Xilinx:ACCL:external_dma_2port:1.0 external_dma_1
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins external_dma_1/ap_clk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins external_dma_1/ap_rst_n]
connect_bd_intf_net [get_bd_intf_pins external_dma_1/m_axi_0] [get_bd_intf_pins axi_crossbar_0/S01_AXI]
Expand Down Expand Up @@ -203,6 +203,8 @@ if { $en_dma != 0 } {

set s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_data ]
set_property -dict [ list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {512} CONFIG.FREQ_HZ {250000000} CONFIG.HAS_BRESP {0} CONFIG.HAS_BURST {0} CONFIG.HAS_CACHE {0} CONFIG.HAS_LOCK {0} CONFIG.HAS_PROT {0} CONFIG.HAS_QOS {0} CONFIG.HAS_REGION {0} CONFIG.HAS_WSTRB {1} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} ] $s_axi
set_property -dict [list CONFIG.ID_WIDTH.VALUE_SRC USER CONFIG.AWUSER_WIDTH.VALUE_SRC USER CONFIG.ARUSER_WIDTH.VALUE_SRC USER] $s_axi
set_property -dict [list CONFIG.ARUSER_WIDTH {4} CONFIG.AWUSER_WIDTH {4} CONFIG.ID_WIDTH {4} ] $s_axi
connect_bd_intf_net [get_bd_intf_ports s_axi_data] [get_bd_intf_pins axi_crossbar_2/S00_AXI]

connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_crossbar_0/aclk]
Expand Down
6 changes: 3 additions & 3 deletions kernels/cclo/tcl/rebuild_bd.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,7 @@ proc create_root_design { netStackType enableDMA enableArithmetic enableCompress
set control_xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 control_xbar ]
set_property -dict [ list CONFIG.NUM_MI {2} ] $control_xbar

source -notrace ./tcl/control_bd.tcl
source -notrace ../tcl/control_bd.tcl
set idcode [expr {$commitHash<<8 | $debugLevel<<6 | $enableExtKrnlStream<<5 | $enableCompression<<4 | $enableArithmetic<<3 | $enableDMA<<2 | ($netStackType == "RDMA" ? 2 : $netStackType == "TCP" ? 1 : 0) }]
create_hier_cell_control [current_bd_instance .] control $debugLevel $idcode

Expand Down Expand Up @@ -232,8 +232,8 @@ proc create_root_design { netStackType enableDMA enableArithmetic enableCompress
save_bd_design

# Create network (de)packetizer
source -notrace ./tcl/rx_bd.tcl
source -notrace ./tcl/tx_bd.tcl
source -notrace ../tcl/rx_bd.tcl
source -notrace ../tcl/tx_bd.tcl
if { $netStackType == "TCP" } {

# TCP interfaces
Expand Down
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