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Host buffer support in sim (#188)
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@quetric
quetric authored Mar 25, 2024
1 parent 343da3e commit fc521c2
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Showing 15 changed files with 264 additions and 140 deletions.
87 changes: 67 additions & 20 deletions driver/xrt/include/accl/simbuffer.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,21 @@

/** @file simbuffer.hpp */

#define DEFAULT_SIMBUFFER_MEMGRP 0
#define ACCL_SIM_DEFAULT_BANK 0

#ifndef ACCL_SIM_NUM_BANKS
#define ACCL_SIM_NUM_BANKS 1
#endif

#ifndef ACCL_SIM_MEM_SIZE_KB
#define ACCL_SIM_MEM_SIZE_KB (256*1024)
#endif

namespace ACCL {
/** Stores the next free address on the simulated device. */
extern addr_t next_free_address;
/** Stores the next free address on the simulated device.
Multiple card memory banks and one host memory bank */
extern addr_t next_free_card_address[ACCL_SIM_NUM_BANKS];
extern addr_t next_free_host_address;

/**
* A buffer that is allocated on a external CCLO emulator or simulator with an
Expand All @@ -53,6 +63,8 @@ template <typename dtype> class SimBuffer : public Buffer<dtype> {
xrt::bo _bo; // Only set if constructed using bo.
xrt::bo internal_copy_bo; // Used to sync bo over zmq
xrt::device _device{}; // Used to create copy buffers
xrt::bo::flags flags; // Flags identifying buffer type
xrt::memory_group memgrp; //bank of buffer has device-side image
bool bo_valid{};

/**
Expand All @@ -61,12 +73,31 @@ template <typename dtype> class SimBuffer : public Buffer<dtype> {
* @param size Size of the buffer to allocate.
* @return addr_t Next free address on the CCLO.
*/
addr_t get_next_free_address(size_t size) {
addr_t address = next_free_address;
addr_t get_next_free_card_address(size_t size, xrt::memory_group memgrp = ACCL_SIM_DEFAULT_BANK) {
if(memgrp > ACCL_SIM_NUM_BANKS){
throw std::invalid_argument("Requested address in invalid memory bank");
}
addr_t address = next_free_card_address[memgrp];
// allocate on 4K boundaries
// not sure how realistic this is, but it does help
// work around some addressing limitations in RTLsim
next_free_card_address[memgrp] += ((addr_t)std::ceil(size / 4096.0)) * 4096;

return address + memgrp*ACCL_SIM_MEM_SIZE_KB*1024;
}

/**
* Get the next free host address available.
*
* @param size Size of the buffer to allocate.
* @return addr_t Next free host address.
*/
addr_t get_next_free_host_address(size_t size) {
addr_t address = next_free_host_address;
// allocate on 4K boundaries
// not sure how realistic this is, but it does help
// work around some addressing limitations in RTLsim
next_free_address += ((addr_t)std::ceil(size / 4096.0)) * 4096;
next_free_host_address += ((addr_t)std::ceil(size / 4096.0)) * 4096;

return address;
}
Expand Down Expand Up @@ -99,11 +130,18 @@ template <typename dtype> class SimBuffer : public Buffer<dtype> {
* @param length Amount of elements in the existing host buffer.
* @param type ACCL datatype of buffer.
* @param context The zmq server of the CCLO to use.
* @param flags The type of buffer to create.
* @param mmegrp The bank in which to allocate the buffer.
*/
SimBuffer(dtype *buffer, size_t length, dataType type,
zmq_intf_context *const context)
zmq_intf_context *const context,
xrt::bo::flags flags = xrt::bo::flags::normal,
xrt::memory_group memgrp = ACCL_SIM_DEFAULT_BANK)
: SimBuffer(buffer, length, type, context,
this->get_next_free_address(length * sizeof(dtype))) {}
flags == xrt::bo::flags::host_only ?
this->get_next_free_host_address(length * sizeof(dtype)) :
this->get_next_free_card_address(length * sizeof(dtype), memgrp),
flags, memgrp) {}

/**
* Construct a new simulated buffer from a simulated BO buffer.
Expand All @@ -119,34 +157,44 @@ template <typename dtype> class SimBuffer : public Buffer<dtype> {
SimBuffer(xrt::bo &bo, xrt::device &device, size_t length, dataType type,
zmq_intf_context *const context)
: SimBuffer(bo.map<dtype *>(), length, type, context,
this->get_next_free_address(length * sizeof(dtype)), bo,
device, true) {}
bo.get_flags() == xrt::bo::flags::host_only ?
this->get_next_free_host_address(length * sizeof(dtype)) :
this->get_next_free_card_address(length * sizeof(dtype), ACCL_SIM_DEFAULT_BANK),
bo, device, true) {}

/**
* Construct a new simulated buffer without an existing host pointer.
*
* @param length Amount of elements to allocate for.
* @param type ACCL datatype of buffer.
* @param context The zmq server of the CCLO to use.
* @param flags The type of buffer to create.
* @param mmegrp The bank in which to allocate the buffer.
*/
SimBuffer(size_t length, dataType type, zmq_intf_context *const context)
: SimBuffer(create_internal_buffer(length), length, type, context) {}
SimBuffer(size_t length, dataType type, zmq_intf_context *const context,
xrt::bo::flags flags = xrt::bo::flags::normal,
xrt::memory_group memgrp = ACCL_SIM_DEFAULT_BANK)
: SimBuffer(create_internal_buffer(length), length, type, context, flags, memgrp) {}

/**
* Construct a new simulated buffer from an existing host pointer at a
* specific physical address. You should generally let ACCL itself decide
* which physical address to use.
*
* @param buffer Host buffer to use.
* @param length Amount of elements in host pointer.
* @param type ACCL datatype of buffer.
* @param context The zmq server of the CCLO to use.
* @param buffer Host buffer to use.
* @param length Amount of elements in host pointer.
* @param type ACCL datatype of buffer.
* @param context The zmq server of the CCLO to use.
* @param address The physical address of the device buffer.
* @param flags The type of buffer to create.
* @param mmegrp The bank in which to allocate the buffer.
*/
SimBuffer(dtype *buffer, size_t length, dataType type,
zmq_intf_context *const context, const addr_t address)
zmq_intf_context *const context, const addr_t address,
xrt::bo::flags flags = xrt::bo::flags::normal,
xrt::memory_group memgrp = ACCL_SIM_DEFAULT_BANK)
: Buffer<dtype>(buffer, length, type, address), zmq_ctx(context),
_bo(xrt::bo()) {
_bo(xrt::bo()), flags(flags), memgrp(memgrp) {
allocate_buffer();
}

Expand All @@ -161,8 +209,7 @@ template <typename dtype> class SimBuffer : public Buffer<dtype> {
: Buffer<dtype>(buffer, length, type, address), zmq_ctx(context),
_bo(bo), _device(device), bo_valid(bo_valid_) {
if (bo_valid) {
internal_copy_bo = xrt::bo(_device, this->_size,
(xrt::memory_group)DEFAULT_SIMBUFFER_MEMGRP);
internal_copy_bo = xrt::bo(_device, this->_size, this->flags, this->memgrp);
}

allocate_buffer();
Expand Down
3 changes: 2 additions & 1 deletion driver/xrt/src/simbuffer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20,5 +20,6 @@

namespace ACCL {
/* Can't define variable in header */
addr_t next_free_address = 0x0;
addr_t next_free_host_address = 0x0;
addr_t next_free_card_address[ACCL_SIM_NUM_BANKS] = {0x0};
}
2 changes: 1 addition & 1 deletion kernels/cclo/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ $(CCLO_ELF): tcl/generate_sw.tcl tcl/associate_elf.tcl $(FW_SOURCES) $(CCLO_XSA)
simdll: $(CCLO_SIMDLL)

$(CCLO_SIMDLL): tcl/generate_sim.tcl elf
$(MAKE) -C ../plugins PLATFORM=$(PLATFORM)
$(MAKE) -C ../plugins PLATFORM=$(PLATFORM) NUM_EXTDMA_AXI=2
vivado -mode batch -source $< -tclargs $(STACK_TYPE) $(EN_DMA) $(EN_ARITH) $(EN_COMPRESS) $(EN_EXT_KRNL) $(SIM_MEM_SIZE_LOG) $(SIM_MEM_LATENCY)
cd ccl_offload_ex/ccl_offload_ex.sim/sim_1/behav/xsim/ && ./compile.sh && ./elaborate.sh

Expand Down
1 change: 0 additions & 1 deletion kernels/cclo/hdl/ccl_offload.v
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Original file line number Diff line number Diff line change
Expand Up @@ -612,7 +612,6 @@ module ccl_offload
.s_axi_data_arqos(s_axi_data_arqos),
.s_axi_data_arready(s_axi_data_arready),
.s_axi_data_arsize(s_axi_data_arsize),
.s_axi_data_aruser(s_axi_data_aruser),
.s_axi_data_arvalid(s_axi_data_arvalid),
.s_axi_data_awaddr(s_axi_data_awaddr),
.s_axi_data_awburst(s_axi_data_awburst),
Expand Down
58 changes: 45 additions & 13 deletions kernels/cclo/tcl/generate_sim.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -120,22 +120,40 @@ if { $en_dma != 0 } {
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_1/BRAM_PORTA] [get_bd_intf_pins sim_mem_1/MEM_PORT_A]
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_1/BRAM_PORTB] [get_bd_intf_pins sim_mem_1/MEM_PORT_B]

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_2
set_property -dict [list CONFIG.SINGLE_PORT_BRAM {0} CONFIG.DATA_WIDTH {512} CONFIG.ECC_TYPE {0} CONFIG.READ_LATENCY $latency] [get_bd_cells axi_bram_ctrl_2]
create_bd_cell -type module -reference sim_mem sim_mem_2
set_property -dict [list CONFIG.MEM_DEPTH_LOG $mem_addr_bits CONFIG.MEM_WIDTH {512} CONFIG.READ_LATENCY $latency] [get_bd_cells sim_mem_2]
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_2/BRAM_PORTA] [get_bd_intf_pins sim_mem_2/MEM_PORT_A]
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_2/BRAM_PORTB] [get_bd_intf_pins sim_mem_2/MEM_PORT_B]

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0
set_property -dict [list CONFIG.NUM_SI {3} CONFIG.NUM_MI {2}] [get_bd_cells axi_crossbar_0]
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_0/M01_AXI] [get_bd_intf_pins axi_bram_ctrl_1/S_AXI]

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_1
set_property -dict [list CONFIG.NUM_SI {3} CONFIG.NUM_MI {1}] [get_bd_cells axi_crossbar_1]
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_1/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_2/S_AXI]

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_2
set_property -dict [list CONFIG.NUM_SI {1} CONFIG.NUM_MI {2}] [get_bd_cells axi_crossbar_2]
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_2/M00_AXI] [get_bd_intf_pins axi_crossbar_0/S02_AXI]
connect_bd_intf_net [get_bd_intf_pins axi_crossbar_2/M01_AXI] [get_bd_intf_pins axi_crossbar_1/S02_AXI]

create_bd_cell -type ip -vlnv Xilinx:ACCL:external_dma:1.0 external_dma_0
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins external_dma_0/ap_clk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins external_dma_0/ap_rst_n]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/m_axi_0] [get_bd_intf_pins axi_crossbar_0/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/m_axi_1] [get_bd_intf_pins axi_crossbar_1/S00_AXI]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/s_axis_s2mm] [get_bd_intf_pins cclo/m_axis_dma0_s2mm]
connect_bd_intf_net [get_bd_intf_pins external_dma_0/m_axis_mm2s] [get_bd_intf_pins cclo/s_axis_dma0_mm2s]

create_bd_cell -type ip -vlnv Xilinx:ACCL:external_dma:1.0 external_dma_1
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins external_dma_1/ap_clk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins external_dma_1/ap_rst_n]
connect_bd_intf_net [get_bd_intf_pins external_dma_1/m_axi_0] [get_bd_intf_pins axi_crossbar_0/S01_AXI]
connect_bd_intf_net [get_bd_intf_pins external_dma_1/m_axi_1] [get_bd_intf_pins axi_crossbar_1/S01_AXI]
connect_bd_intf_net [get_bd_intf_pins external_dma_1/s_axis_s2mm] [get_bd_intf_pins cclo/m_axis_dma1_s2mm]
connect_bd_intf_net [get_bd_intf_pins external_dma_1/m_axis_mm2s] [get_bd_intf_pins cclo/s_axis_dma1_mm2s]

Expand Down Expand Up @@ -185,33 +203,47 @@ if { $en_dma != 0 } {

set s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi_data ]
set_property -dict [ list CONFIG.ADDR_WIDTH {64} CONFIG.DATA_WIDTH {512} CONFIG.FREQ_HZ {250000000} CONFIG.HAS_BRESP {0} CONFIG.HAS_BURST {0} CONFIG.HAS_CACHE {0} CONFIG.HAS_LOCK {0} CONFIG.HAS_PROT {0} CONFIG.HAS_QOS {0} CONFIG.HAS_REGION {0} CONFIG.HAS_WSTRB {1} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} ] $s_axi
connect_bd_intf_net [get_bd_intf_ports s_axi_data] [get_bd_intf_pins axi_crossbar_0/S02_AXI]
connect_bd_intf_net [get_bd_intf_ports s_axi_data] [get_bd_intf_pins axi_crossbar_2/S00_AXI]

connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_crossbar_0/aclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins axi_crossbar_0/aresetn]
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_crossbar_1/aclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins axi_crossbar_1/aresetn]
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_crossbar_2/aclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins axi_crossbar_2/aresetn]
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_bram_ctrl_1/s_axi_aclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins axi_bram_ctrl_1/s_axi_aresetn]
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins axi_bram_ctrl_2/s_axi_aclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins axi_bram_ctrl_2/s_axi_aresetn]

# #assign addresses and set ranges
save_bd_design
assign_bd_address

set_property offset $memsize [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_1_Mem0}]
set_property offset $memsize [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_1_Mem0}]
set_property offset $memsize [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_1_Mem0}]
set_property offset 0x0000000000000000 [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_0_Mem0}]
set_property offset 0x0000000000000000 [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property offset 0x0000000000000000 [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property offset [expr { 0*$memsize }] [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_0_Mem0}]
set_property offset [expr { 1*$memsize }] [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_1_Mem0}]
set_property offset [expr { 2*$memsize }] [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_2_Mem0}]
set_property range $memsize [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_0_Mem0}]
set_property range $memsize [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_1_Mem0}]
set_property range $memsize [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_2_Mem0}]

set_property offset [expr { 0*$memsize }] [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property offset [expr { 1*$memsize }] [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_1_Mem0}]
set_property offset [expr { 2*$memsize }] [get_bd_addr_segs {external_dma_0/m_axi_1/SEG_axi_bram_ctrl_2_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_0/m_axi_0/SEG_axi_bram_ctrl_1_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_0/m_axi_1/SEG_axi_bram_ctrl_2_Mem0}]

set_property offset [expr { 0*$memsize }] [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property offset [expr { 1*$memsize }] [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_1_Mem0}]
set_property offset [expr { 2*$memsize }] [get_bd_addr_segs {external_dma_1/m_axi_1/SEG_axi_bram_ctrl_2_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_0_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_1/m_axi_0/SEG_axi_bram_ctrl_1_Mem0}]
set_property range $memsize [get_bd_addr_segs {s_axi_data/SEG_axi_bram_ctrl_1_Mem0}]
set_property range $memsize [get_bd_addr_segs {external_dma_1/m_axi_1/SEG_axi_bram_ctrl_2_Mem0}]

group_bd_cells external_memory [get_bd_cells axi_bram_ctrl_*] [get_bd_cells sim_mem_*] [get_bd_cells axi_crossbar_0]
group_bd_cells external_memory [get_bd_cells axi_bram_ctrl_*] [get_bd_cells sim_mem_*] [get_bd_cells axi_crossbar_*]
group_bd_cells dma [get_bd_cells external_dma_*] [get_bd_cells cyt_dma_0] [get_bd_cells cyt_dma_adapter_0]

}
Expand Down Expand Up @@ -263,7 +295,7 @@ if { $stacktype == "RDMA" } {
connect_bd_intf_net [get_bd_intf_pins dummy_cyt_rdma_stack/recv_data] [get_bd_intf_pins cclo/s_axis_eth_rx_data]
connect_bd_intf_net [get_bd_intf_pins cclo/m_axis_eth_tx_data] [get_bd_intf_pins dummy_cyt_rdma_stack/send_data]

set_property -dict [list CONFIG.NUM_SI {4}] [get_bd_cells external_memory/axi_crossbar_0]
set_property -dict [list CONFIG.NUM_SI {2}] [get_bd_cells external_memory/axi_crossbar_2]

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 cyt_wr_dma
set_property -dict [list CONFIG.c_enable_mm2s {0} CONFIG.c_include_s2mm_dre {true} CONFIG.c_s2mm_support_indet_btt {true} ] [get_bd_cells cyt_wr_dma]
Expand All @@ -272,7 +304,7 @@ if { $stacktype == "RDMA" } {
connect_bd_intf_net [get_bd_intf_pins cyt_wr_dma/S_AXIS_S2MM] [get_bd_intf_pins dummy_cyt_rdma_stack/wr_data]
connect_bd_intf_net [get_bd_intf_pins dummy_cyt_rdma_stack/wr_cmd] [get_bd_intf_pins cyt_wr_dma/S_AXIS_S2MM_CMD]
connect_bd_intf_net [get_bd_intf_pins dummy_cyt_rdma_stack/wr_sts] [get_bd_intf_pins cyt_wr_dma/M_AXIS_S2MM_STS]
connect_bd_intf_net [get_bd_intf_pins cyt_wr_dma/M_AXI_S2MM] [get_bd_intf_pins external_memory/axi_crossbar_0/S03_AXI]
connect_bd_intf_net [get_bd_intf_pins cyt_wr_dma/M_AXI_S2MM] [get_bd_intf_pins external_memory/axi_crossbar_2/S01_AXI]
connect_bd_net [get_bd_ports ap_clk] [get_bd_pins cyt_wr_dma/m_axi_s2mm_aclk] [get_bd_pins cyt_wr_dma/m_axis_s2mm_cmdsts_awclk]
connect_bd_net [get_bd_ports ap_rst_n] [get_bd_pins cyt_wr_dma/m_axi_s2mm_aresetn] [get_bd_pins cyt_wr_dma/m_axis_s2mm_cmdsts_aresetn]

Expand Down
1 change: 1 addition & 0 deletions kernels/plugins/Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ TARGET=ip
PLATFORM ?= xilinx_u280_xdma_201920_3
DEBUG ?= none
STACK_TYPE ?= UDP
NUM_EXTDMA_AXI ?= 1

ifeq (u250,$(findstring u250, $(PLATFORM)))
FPGAPART=xcu250-figd2104-2L-e
Expand Down
4 changes: 2 additions & 2 deletions kernels/plugins/external_dma/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -16,12 +16,12 @@
# *******************************************************************************/

DEVICE ?= xcu280-fsvh2892-2L-e
NUM_DMA ?= 1
NUM_EXTDMA_AXI ?= 1

all: external_dma.xo

external_dma.v kernel.xml &: gen_files.py
python3 $< -n $(NUM_DMA)
python3 $< -n $(NUM_EXTDMA_AXI)

external_dma.xo: bd.tcl kernel.xml external_dma.v
vivado -mode batch -source $< -notrace -tclargs $(DEVICE)
2 changes: 2 additions & 0 deletions test/host/xrt/CMakeLists.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,8 @@ cmake_minimum_required(VERSION 3.9)
project(xrt_test)

set(CMAKE_CXX_STANDARD 17)
set(ACCL_SIM_NUM_BANKS 2 CACHE STRING "Number of ACCL simulator memory banks (must correspond to simdll)")
set(ACCL_SIM_MEM_SIZE_KB 262144 CACHE STRING "Size of ACCL simulator memory, in KB (must correspond to simdll)")

#GTest config
include(FetchContent)
Expand Down
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