Unconditional branch support #20
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| extend extend | ||
| ( .in ( instr[31:20] ) | ||
| , .imm_ext ( imm_ext ) | ||
| ); |
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Technically this module is not really needed since instruction decode module already implements this, but does not expose the ImmExt; i think we can keep this as is for now though, I will remove this during beq implementation.
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I removed extend in #27
| @@ -6,5 +6,6 @@ | |||
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| typedef logic [`PROCESSOR_BITNESS-1:0] instr_t; | |||
| typedef logic [`PROCESSOR_BITNESS-1:0] addr_t; | |||
| typedef logic [`PROCESSOR_BITNESS-1:0] imm_t; | |||
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i think this is somewhat unnecessary. i think there should be instr_t, addr_t and data_t; these exist exclusively to enhance readability and do not really carry functional meaning. The idea is to use:
instr_twhen we are sure the wire will be used to carry exclusively instructions, such as input to instruction decode;addr_twhen we are sure the wire is used to carry exclusively address (e.g.pc)data_tfor all other cases (e.g. sending data back to register fire after computation -- can be both address and instruction, as well as mathematical result)
| assign pc_mux_in[0] = pc_target; | ||
| assign pc_mux_in[1] = pc_plus_4; |
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Pretty sure this is the other way around -- increment should be on 0 and jump on 1
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This was fixed on #27
| assign pc_mux_in[0] = pc_target; | ||
| assign pc_mux_in[1] = pc_plus_4; | ||
| mux #( .INPUT_COUNT ( 2 ), .INPUT_WIDTH ( `PROCESSOR_BITNESS ) ) pc_mux | ||
| ( .sel ( cfsm__pc_src ) | ||
| , .in ( pc_mux_in ) | ||
| , .out ( pc_next ) | ||
| ); |
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Also considering a case statement here instead of mux module. Would also like to use constants for 0 and 1 cases, for better readability.
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I poped the vcd's for the testbenches into #27 |
Extended #12 with unconditional branch support via
pc_srcsignal from the control FSM.