gui: add gui/open_yosys targets

[oharboe]

Useful when viewing a netlist with blackboxed modules where there's no .odb file in parallel synthesi

[oharboe]

@maliberty Recently write_db will no longer write out .odb files with blackboxed submodules, I believe an intentional sanity check, so this covers the view timing for netlist use-case.

[Copilot]

Pull request overview

This PR adds support for opening Verilog netlist files (.v) in the OpenROAD GUI, which is useful when viewing netlists with blackboxed modules during hierarchical synthesis where no .odb file exists yet.

Changes:

• Added support for reading Verilog files directly in the GUI
• Created a new gui_yosys target for viewing Yosys synthesis outputs
• Extended the file opening logic to handle .v files alongside existing .odb and .def formats

Reviewed changes

Copilot reviewed 4 out of 4 changed files in this pull request and generated 1 comment.

File	Description
flow/scripts/variables.mk	Exports RESULTS_V variable to track Verilog files in results directory
flow/scripts/open.tcl	Adds conditional logic to read Verilog files with LEF libraries when no ODB/DEF exists
flow/designs/asap7/minimal/README.md	Documents the new gui_yosys target for viewing netlists with blackboxed modules
flow/Makefile	Registers the gui_yosys shortcut and enables GUI opening for all .v files in results

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[oharboe]

@maliberty unrelated mock-cpu (mesochronous-fifo) QoR failures:

14:33:49  [ERROR] finish__timing__setup__tns fail test: -2362.01 >= -2230

[maliberty]

Please explain the write_db issue. You probably need to merge master for the metrics issue.

[oharboe]

Please explain the write_db issue. You probably need to merge master for the metrics issue.

If I use SYNTH_BLACKBOXES for a module, write_db no longer will save a .odb file, but fails.

I thought this was an intentional sanity check?

[oharboe]

did a merge, pr head passed, pr merge failed.

@maliberty so master is a bit flaky now?

[maliberty]

In what way does write_db fail? I'm not sure what sanity check you are describing.

[oharboe]

It says there is no master for the blackboxed module, as I recall.

[oharboe]

Example:

$ make DESIGN_CONFIG=designs/asap7/aes/config.mk SYNTH_BLACKBOXES=aes_rcon
[deleted]
[WARNING STA-0198] ./results/asap7/aes/base/1_2_yosys.v line 102385, module aes_rcon not found. Creating black box for \u0.r0 .
[ERROR ORD-2013] instance u0.r0 LEF master aes_rcon not found.

[oharboe]

@maliberty Merge? I think this is a nice addition, even if The-OpenROAD-Project/OpenROAD#9413 is/should be fixed.

[maliberty]

That error isn't related to write_db. It is a sanity check as you can't do physical design without a LEF to give a physical description. Do you not have a LEF or have you not loaded it?

[oharboe]

That error isn't related to write_db. It is a sanity check as you can't do physical design without a LEF to give a physical description. Do you not have a LEF or have you not loaded it?

Neither: I'm doing hierarchical synthesis.

Hierarchical Synthesis with Bazel-ORFS

The Concept

Hierarchical synthesis breaks a large design into parallelizable chunks to save time and memory. Instead of a single "flat" synthesis run, you treat sub-modules as independent entities.

1. Parallel Synthesis

Define a list of modules to be synthesized simultaneously. Bazel handles the scheduling, ensuring each module is mapped to gates in its own isolated process.

2. Blackboxing and synthesizing each module separately as a top module

Each module in that list is synthesized as a top module.

When synthesizing each Top module, use SYNTH_BLACKBOXES to list all other modules except the top module. blackboxing modules that don't exist in the design gives a warning in yosys but is harmless.

• Effect: The synthesizer treats sub-modules as empty shells with defined ports.
• Benefit: The Top-level run finishes in seconds because it only synthesizes the "glue logic" connecting the blocks.

3. Netlist Assembly

Since the outputs are structural Verilog, the final step is a simple file concatenation.

cat sub_module_A.v sub_module_B.v top_level.v > final_netlist.v