[ERROR ORD-2013] instance u0.r0 LEF master aes_rcon not found.

[oharboe]

This surprised me and it breaks gui_synth for hierarchical synthesis. Is this an intentional change? It makes sense to me as a sanity check, perhaps?

This warning was made into an error in 435cbd5

Example:

$ make DESIGN_CONFIG=designs/asap7/aes/config.mk SYNTH_BLACKBOXES=aes_rcon
[deleted]
[WARNING STA-0198] ./results/asap7/aes/base/1_2_yosys.v line 102385, module aes_rcon not found. Creating black box for \u0.r0 .
[ERROR ORD-2013] instance u0.r0 LEF master aes_rcon not found.

Originally posted by @oharboe in The-OpenROAD-Project/OpenROAD-flow-scripts#3857 (comment)

git bisect run script:

git cherry-pick 4bee233fa133bc799bcd79aab11e390d6d51b264 || git cherry-pick --abort
git submodule update --recursive
bazelisk run //:install --//:platform=gui || exit 125
make -C ../../flow DESIGN_CONFIG=designs/asap7/aes/config.mk SYNTH_BLACKBOXES=aes_rcon do-1_synth

[gadfort]

It seems to me that this error is correct, without the LEF there really is nothing openroad to do with this object.

[oharboe]

My use case is male gui_synth w hierarchical synthesis and there blackboxed modules is idomatic andI believe it is a matter of choice if one wants .odb to support/represent this or not.

[maliberty]

There is nothing to visualize in the GUI at synthesis. Is this just to look at timing paths? If so would standalone sta suffice?

[oharboe]

I use all the OpenROAD GUI features to study timing structure, OpenSTA is text only.

I can readily read in .odb previously and 1_2_yosys.v now in the GUI. Works great!

[oharboe]

OpenROAD is the OpenSTA GUI as far as I am concerned.

Is there another OpenSTA GUI?

[maliberty]

The challenge is that most of OR expects there to be a LEF and recently we had a crash when one was missing. There is a narrow use model of sta & gui only that might work but anything else is dangerous. Its tricky to enable one but not the other.

Is it possible to make a placeholder LEF for your black box?

[oharboe]

Does this danger exist when I read the .v file?

For me this has worked very well. Cant recall crashes, when I see them I generally report them.

[oharboe]

Conceptually, I think about blackboxed verilog modules pins as top level pins. Doesnt OpenSTA too?