2020-1-capstone

Yonsei University Team Acafela 2020-1 Software Capstone Design Repository

Testing NPU architectures via measuring integrated trade-offs

This repository is about 2020-1 capstone design, implementing WS- and OS-architecture NPU on PyNQ-Z2 using Vivado HLS and Vivado and measuring integrated trade-offs

Vivado HLS

We implemented weight stationary architecture and output stationary architecture using C language. Vivado HLS converts the C source code to IP Core.

Vivado

Vivado converts the IP Core to bitstream. Power report of Vivado shows the power estimation according to the logic implented by us.

Jupyter notebook

We overlaied the bitstream to the PyNQ-Z2 using python module and measured the processing time of 1-D convolution operation which is accelerated by ws- and os- architecture NPU.

Contributors

Junhyeok Kim (Yonsei University)
Yoonsuk Jung (Yonsei University)
Hyeonkyu Kim (Yonsei University)

Jounghoo Lee (TA, High Performance Computing Platform Lab (https://hpcp.yonsei.ac.kr/), Yonsei Univeristy)
Prof. Youngsok Kim (High Performance Computing Platform Lab (https://hpcp.yonsei.ac.kr/), Yonsei Univeristy)