PolarFire SoC eMMC/SD improvements and RISC-V boot code unification#657
Merged
danielinux merged 4 commits intowolfSSL:masterfrom Dec 30, 2025
Merged
PolarFire SoC eMMC/SD improvements and RISC-V boot code unification#657danielinux merged 4 commits intowolfSSL:masterfrom
danielinux merged 4 commits intowolfSSL:masterfrom
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…. Refactor the RISC-V boot/vector code for use on both 32-bit and 64-bit architectures.
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…Yocto Linux is fully working now!
danielinux
approved these changes
Dec 30, 2025
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PolarFire SoC eMMC/SD improvements and RISC-V boot code unification
Summary
This PR improves the PolarFire SoC (MPFS250) support with eMMC/SD driver stabilization, DMA read support, and fixes a Yocto Linux boot issue. Additionally, it refactors the RISC-V boot code to unify 32-bit and 64-bit architectures into a single codebase.
Changes
PolarFire SoC eMMC/SD Improvements
RISC-V Boot Code Refactoring
__riscv_xlenconditional compilation:src/boot_riscv.c(removedboot_riscv64.c)src/boot_riscv_start.S(removedboot_riscv64_start.S)src/vector_riscv.S(removedvector_riscv64.S)hal/riscv.hheader with common RISC-V definitions (CSRs, register sizes, trap handling macros)Yocto Linux Boot Fix
hartidwasn't being properly passed to the Linux kernela0= hartid of the boot corea1= physical address of the device tree blob (DTB)satp= 0 (MMU disabled)tpregisterDocumentation
Files Changed
hal/mpfs250.chal/mpfs250.hhal/riscv.hsrc/boot_riscv.csrc/boot_riscv_start.Sboot_riscv64_start.S)src/vector_riscv.Ssrc/boot_riscv64.csrc/vector_riscv64.Ssrc/update_disk.csrc/x86/common.cinclude/hal.harch.mkdocs/Targets.mdTesting