hal: stm32u5: Fix FLASH_CR_PNB_MASK#632
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This commit update the PNB (Secure page number selection) mask according to reference manual update. In RM0456 document update (Rev.3 -> Rev.4), PNB bits in FLASH_SECCR (Section 7.9.10) has been updated from 7 bits to 8 bits for the support of 2MB in single bank. Logically, devices which flash is lesser than 2MB will ignore bit 10 because of the definition (Reserved). However, for other devices, NUCLEO-U5A5ZJ-Q for example, page calculation will be wrong because bit 10 is __always 1__ after flipping by: reg = *cr & (~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER)); Without this commit, some devices will be failed to erase pages of flash, and lead to update failure. Signed-off-by: Elwin Huang <s09289728096@gmail.com>
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Thank you @s09289728096 for pointing this out! Its been fixed in PR #633 |
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This commit update the PNB (Secure page number selection) mask according by reference manual to fix the compatible for devices with larger size flash.
According to latest RM0456 document (Rev.6), FLASH_SECCR register definitions shown below:
PNB bits in FLASH_SECCR has been updated from 7 bits to 8 bits for the support of 2MB in single bank.
Logically, devices which flash is lesser than 2MB will ignore bit 10 because of the definition (see below).
(Rev.3 definitions)
Without this commit, page calculation will be wrong because bit 10 is always 1 after flipping by:
wolfBoot/hal/stm32u5.c
Line 210 in a8afa74
Test on NUCLEO-U5A5ZJ-Q (2MB per bank) and NUCLEO-U575ZJ-Q (1MB per bank)