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Hetero cgra glb conns #146

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merged 2 commits into from
Feb 11, 2025
Merged

Hetero cgra glb conns #146

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eb2c2fe
Fix E64 write hacks for sparse
mcoduoza Jan 24, 2025
7961414
Merge branch 'mapping_to_cgra' into hetero-cgra-glb-conns
mcoduoza Feb 5, 2025
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9 changes: 7 additions & 2 deletions sam/onyx/hw_nodes/glb_node.py
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from sam.onyx.hw_nodes.hw_node import *
import os


class GLBNode(HWNode):
Expand Down Expand Up @@ -92,9 +93,11 @@ def connect(self, other, edge, kwargs=None):
raise NotImplementedError(f'Cannot connect GLBNode to {other_type}')
elif other_type == WriteScannerNode:
wr_scan = other.get_name()
include_E64_HW = "INCLUDE_E64_HW" in os.environ and os.environ.get("INCLUDE_E64_HW") == "1"
io2f_port_name = "io2f_17_0" if include_E64_HW else "io2f_17"
new_conns = {
'glb_to_wr_scan': [
([(self.data, "io2f_17"), (wr_scan, "block_wr_in")], 17),
([(self.data, io2f_port_name), (wr_scan, "block_wr_in")], 17),
]
}
return new_conns
Expand Down Expand Up @@ -125,9 +128,11 @@ def connect(self, other, edge, kwargs=None):
return conns_remapped
elif other_type == PassThroughNode:
pass_through = other.get_name()
include_E64_HW = "INCLUDE_E64_HW" in os.environ and os.environ.get("INCLUDE_E64_HW") == "1"
io2f_port_name = "io2f_17_0" if include_E64_HW else "io2f_17"
new_conns = {
'glb_to_pass_through': [
([(self.data, "io2f_17"), (pass_through, "stream_in")], 17),
([(self.data, io2f_port_name), (pass_through, "stream_in")], 17),
]
}
return new_conns
Expand Down
5 changes: 4 additions & 1 deletion sam/onyx/hw_nodes/read_scanner_node.py
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from numpy import block
from sam.onyx.hw_nodes.hw_node import *
import os


class ReadScannerNode(HWNode):
Expand Down Expand Up @@ -54,9 +55,11 @@ def connect(self, other, edge, kwargs=None):
other_data = other.get_data()
other_ready = other.get_ready()
other_valid = other.get_valid()
include_E64_HW = "INCLUDE_E64_HW" in os.environ and os.environ.get("INCLUDE_E64_HW") == "1"
f2io_port_name = "f2io_17_0" if include_E64_HW else "f2io_17"
new_conns = {
'rd_scan_to_glb': [
([(rd_scan, "block_rd_out"), (other_data, "f2io_17")], 17),
([(rd_scan, "block_rd_out"), (other_data, f2io_port_name)], 17),
]
}
return new_conns
Expand Down
3 changes: 3 additions & 0 deletions sam/onyx/hw_nodes/stream_arbiter_node.py
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Original file line number Diff line number Diff line change
@@ -1,4 +1,5 @@
from sam.onyx.hw_nodes.hw_node import *
import os


class StreamArbiterNode(HWNode):
Expand Down Expand Up @@ -36,6 +37,8 @@ def connect(self, other, edge, kwargs=None):
other_data = other.get_data()
other_ready = other.get_ready()
other_valid = other.get_valid()
include_E64_HW = "INCLUDE_E64_HW" in os.environ and os.environ.get("INCLUDE_E64_HW") == "1"
f2io_port_name = "f2io_17_0" if include_E64_HW else "f2io_17"
new_conns = {
'stream_arbiter_to_glb': [
([(stream_arb, "stream_out"), (other_data, "f2io_17")], 17),
Expand Down