🌟 I'm an Application Engineer at Synopsys, working on VLSI Physical Design, PPA improvements, Design convergence and flow development.
💡 I'm passionate about VLSI, Digital Design, Embedded Systems, and open-source silicon.

• 🚀 Warp-V CPU Enhancements – GSoC '20 & '21 — RV32FD + B-extension integration, Multicore CPU interconnect development,, Visual debug, TL-Verilog.
• Medium Blog post - About TL-Verilog
• Medium Blog post - Cloud FPGA's and debugging using Visual-debug
• 🔬 Fast & Optimized DNN Architecture on FPGAs — Achieved 256 MHz with 97% accuracy and interfaced camera using Artix-7 FPGAs.
• 🧠 Bit Manipulation in RISC-V on FPGA — Custom ISA design and paper publication
• 🔧 Python & Tcl Scripting Automation — Used at Synopsys to streamline flows and debug testcases and won Innovation Award in Synopsys All-Hands :)

• Synopsys – Application Engineer (Oct 2021 – Present)

  • PPA, timing analysis, convergernce, new-features flow devlopment for advanced tech nodes.
  • Supporting Customer with Fusion Compiler tool for Design Planning and PnR domain.
  • Python and Tcl scripting automation for productivity and design closure.

• Google Summer of Code – Contributor (2020, 2021) with FOSSi Foundation

  • RISC-V enhancements on WARP-V, Archiectural improvement in manycore interconnect, and AWS F1 FPGA deployments.

• Mentored over ~250 Students at VSD's MYTH workshop for 6 iterations.

• Fast and Optimized DNN and Convolution Architecture — IIETA (2025)
• Bit Manipulation Instruction on RISC-V using FPGAs — IEEE CSNT Conference (2020)

• Languages: Verilog, TL-Verilog, Python, C++, TCL
• Tools: Fusion Compiler, Vivado, Git, Linux, Make
• Domains: FPGA Prototyping, VLSI Physical Design, SoC Debug, DNN on FPGAs

• 💼 LinkedIn
• 📫 Email: [email protected]

⭐ “Building a better silicon world, one bit at a time!”