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Issues list

verilog-warn-fatal ignored in batch mode
#1886 opened Nov 21, 2024 by techdude
1
Installation problem
#1871 opened Mar 29, 2024 by 1371906755
1
import packages not working in emacs.
#1864 opened Feb 19, 2024 by deepak00agarwal
1
Slow with many curly braces ({)
#1860 opened Jan 29, 2024 by richyliu
1
Port Coercion Issue on AUTOINPUT
#1859 opened Jan 25, 2024 by ramyamohandoss
7
RFE: option to have AUTORESET reset flops to x rather than 0
#1839 opened Aug 30, 2023 by jwise
1
Issue when using \ followed by "
#1831 opened Jun 21, 2023 by LapinFou
3
2-D array in AUTO_TEMPLATE getting wrong subscript if [][] is used
#1825 opened Mar 3, 2023 by Grmarder
2
What magic sauce is required to indent typedef's correctly?
#1823 opened Feb 21, 2023 by shareefj
2
Syntax highlighting confused by certain type of comment block
#1822 opened Feb 7, 2023 by jwcollins
@gmlarumbe
6
Reversion of bug 1257: Indentation within generate construct after always block is wrong if generate/endgenerate omitted
#1820 opened Jan 17, 2023 by dbhopper
@gmlarumbe
2
Interfaces from AUTOINST are not propagated as ports
#1816 opened Oct 6, 2022 by sarava49
2
Verilog-mode with LSP?
#1814 opened Sep 28, 2022 by unfrostedpoptart
2
AUTOOUTPUTEVERY and AUTOWIRE creates duplicate definitions for signals
#1812 opened Sep 22, 2022 by engrvns
2
verilog-mode-map rebinds delete and backspace keys
#1772 opened Jun 12, 2022 by bjourne
3
Is there a variable to control in which column a port name appears?
#1758 opened Dec 28, 2021 by cswfb
4
AUTOINPUT can not create signal with nettype
#1754 opened Nov 30, 2021 by kopinions
1
Fontifying of variable names in declarations not working correctly highlighting
#1752 opened Nov 11, 2021 by fnJeff
6
Improving the AUTOINST handling of signed ports
#1750 opened Nov 11, 2021 by fnJeff
1
Indenting mismatch between verilog-auto and indent region with non-default verilog-cexp-indent
#1697 opened Oct 3, 2020 by abradd
No hierarchical autocompletion feature
#1687 opened Aug 13, 2020 by Khaled-Ismail
1
Use of Ordered AUTO_TEMPLATEs to simplify code integration enhancement
#1673 opened Jun 6, 2020 by engrvns
3
AUTOASSIGNMODPORT and AUTOASSIGNMODPORT direction autos feature
#1668 opened Apr 24, 2020 by marmarjohnson
1
Replacing instance port parameters with it's values in parent module ports - An issue with usage of verilog-auto-inst-param-value
#1667 opened Apr 21, 2020 by engrvns
2
Wrong statement continue alignment. indents
#1495 opened Sep 1, 2019 by veripoolbot
4
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