Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Adding Number of Logic levels and number of timing graph levels to ti… #2383

Open
wants to merge 2 commits into
base: openfpga
Choose a base branch
from
Open

Adding Number of Logic levels and number of timing graph levels to ti… #2383

wants to merge 2 commits into from

Conversation

behnam-rs
Copy link

…ming setup and hold reports

Description

Adding Number of Logic levels and number of timing graph levels to timing setup and hold reports

Related Issue

Motivation and Context

How Has This Been Tested?

We have tested via some manual small design.

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool external_libs labels Aug 31, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
external_libs VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@behnam-rs @miladeb8