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Feature: complete implementation of AVR32 disassembler
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uxmal committed Dec 11, 2023
1 parent bfd52ef commit 434ab82
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Showing 19 changed files with 93,878 additions and 93,584 deletions.
579 changes: 512 additions & 67 deletions src/Arch/Avr/Avr32/Avr32Disassembler.cs

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309 changes: 303 additions & 6 deletions src/Arch/Avr/Avr32/Avr32Rewriter.cs

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15 changes: 13 additions & 2 deletions src/Arch/Avr/Avr32/MemoryOperand.cs
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ private MemoryOperand(PrimitiveType dt)
public RegisterStorage? Base { get; private set; }
public int Offset { get; private set; }
public RegisterStorage? Index { get; private set; }
public RegisterPart IndexPart { get; private set; }
public int Shift { get; private set; }
public bool PostIncrement { get; private set; }
public bool PreDecrement { get; private set; }
Expand Down Expand Up @@ -71,13 +72,19 @@ internal static MachineOperand PreDec(PrimitiveType dt, RegisterStorage reg)
return mem;
}

public static MachineOperand Indexed(PrimitiveType dt, RegisterStorage baseReg, RegisterStorage x, int shift)
public static MachineOperand Indexed(
PrimitiveType dt,
RegisterStorage baseReg,
RegisterStorage x,
int shift,
RegisterPart part = RegisterPart.All)
{
var mem = new MemoryOperand(dt)
{
Base = baseReg,
Index = x,
Shift = shift
Shift = shift,
IndexPart = part,
};
return mem;
}
Expand All @@ -101,6 +108,10 @@ protected override void DoRender(MachineInstructionRenderer renderer, MachineIns
if (Index != null)
{
renderer.WriteString(Index.Name);
if (IndexPart != RegisterPart.All)
{
renderer.WriteString(IndexPart.Format());
}
if (Shift > 0)
{
renderer.WriteFormat("<<{0}", Shift);
Expand Down
279 changes: 206 additions & 73 deletions src/Arch/Avr/Avr32/Mnemonic.cs
Original file line number Diff line number Diff line change
Expand Up @@ -28,95 +28,228 @@ public enum Mnemonic
{
invalid,

mov,
eor,
ld_w,
st_w,
lddpc,
sub,
rsub,
mcall,
pushm,
ld_ub,
br,
movh,
cp_b,
lddsp,
stdsp,
cp_w,
icall,
popm,
ld_sh,
ld_uh,
st_b,
rcall,
lsr,
rjmp,
lsl,
or,
stm,
abs,
st_h,
st_d,
ret,
sr,
acall,
acr,
adc,
add,
addabs,
subf,
addhh_w,
and,
andnot,
tst,
casts_h,
andh,
andl,
andn,
asr,
bfexts,
bfextu,
bfins,
bld,
br,
breakpoint,
brev,
bst,
cache,
casts_b,
casts_h,
castu_b,
castu_h,
cbr,
clz,
com,
cop,
cp_b,
cp_h,
cp_w,
cpc,
csrf,
csrfcz,
divs,
divu,
eor,
eorh,
eorl,
frs,
icall,
incjosp,
ld_d,
ld_sb,
ld_sh,
ld_ub,
ld_uh,
ld_w,
ldc_d,
ldc_w,
ldc0_d,
ldc0_w,
ldcm_d,
ldcm_w,
lddpc,
lddsp,
ldins_b,
ldins_h,
ldm,
ldmts,
ldswp_sh,
ldswp_uh,
ldswp_w,
lsl,
lsr,
mac,
machh_d,
machh_w,
macs_d,
macsathh_w,
macu_d,
macwh_d,
max,
mcall,
memc,
mems,
memt,
mfdr,
mfsr,
min,
mov,
movh,
mtdr,
mtsr,
mul,
mulhh_w,
mulnhh_w,
mulnwh_d,
muls_d,
mulsathh_h,
mulsathh_w,
mulsatrndhh_h,
mulsatrndwh_w,
mulsatwh_w,
mulu_d,
mulwh_d,
musfr,
mustr,
mvcr_d,
mvcr_w,
mvrc_d,
mvrc_w,
neg,
nop,
or,
orh,
orl,
pabs_sb,
pabs_sw,
packsh_sb,
packsh_ub,
packw_sh,
padd_b,
padd_h,
paddh_sh,
paddh_ub,
padds_sb,
padds_sh,
padds_ub,
padds_uh,
paddsub_h,
paddsub_sh,
paddsubh_sh,
paddsubs_sh,
paddsubs_uh,
paddx_h,
paddxh_sh,
paddxs_sh,
paddxs_uh,
pasr_b,
pasr_h,
pavg_sh,
pavg_ub,
plsl_b,
plsl_h,
plsr_b,
plsr_h,
pmax_sh,
pmax_ub,
pmin_sh,
pmin_ub,
popjc,
popm,
pref,
psad,
psub_b,
psub_h,
psubadd_h,
psubaddh_sh,
psubadds_sh,
psubadds_uh,
psubh_sh,
psubh_ub,
psubs_sb,
psubs_sh,
psubs_ub,
psubs_uh,
psubx_h,
psubxh_sh,
psubxs_sh,
psubxs_uh,
punpcksb_h,
punpckub_h,
pushjc,
pushm,
rcall,
ret,
retd,
rete,
retj,
rets,
retss,
rjmp,
rol,
ror,
rsub,
satadd_h,
satadd_w,
satrnds,
satrndu,
sats,
satsub_h,
satsub_w,
satu,
sbc,
sbr,
scall,
scr,
sleep,
sr,
sscall,
ssrf,
st_b,
st_d,
st_h,
st_w,
stc_d,
stc_w,
stc0_d,
stc0_w,
stcm_d,
stcm_w,
stcond,
stdsp,
sthh_w,
stm,
stmts,
stswp_h,
stswp_w,
sub,
subhh_w,
swap_b,
swap_bh,
swap_h,
tbnz,
mul,
sbr,
ld_sb,
asr,
acr,
ldm,
cbr,
ld_d,
adc,
acall,
andl,
andh,
satsub_w,
stcond,
sbc,
cp_h,
bfextu,
bfexts,
divs,
divu,
mulu_d,
muls_d,
macu_d,
macs_d,
max,
min,
orl,
orh,
clz,
bld,
subf,
bst,
eorl,
eorh,
nop,
sync,
tlbr,
tlbs,
tlbw,
tnbz,
tst,
xchg,
sats,
satu,
}
}
}
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